front.v.bak

FPGA设计中乒乓设计的源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:15:57 12/26/07
// Design Name:    
// Module Name:    front
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module front(clk_5m,rst, nd, indata, a, b, rdy_a, rdy_b);
    input clk_5m;
	 input rst;
    input nd;
    input [15:0] indata;
    output [15:0] a;
    output [15:0] b;
    output rdy_a;
    output rdy_b;

	 reg [15:0] a;
	 reg [15:0] b;
	 reg rdy_a;
	 reg rdy_b;

    reg state;

	 always @(posedge rst or posedge clk_5m)
	 begin
	  if(rst)
	    begin
	    rdy_a<=0;
		 rdy_b<=0;
		 state<=0;
		 end
	  else
	   begin
	    case(state)
		 1'b0:
		   begin
			if(nd==1)
			  begin
			  a<=indata;
			  rdy_a<=1;
			  rdy_b<=0;
			  state<=1'b1;
			  end
			end
		 1'b1:
		   begin
			if(nd==1)
			  begin
			   b<=indata;
				rdy_b<=1;
				rdy_a<=0;
				state<=1'b0;
			  end
			 end
		  endcase
		  if(rdy_a==1)rdy_a<=0;
		  if(rdy_b==1)rdy_b<=0;
		 end
	  end

endmodule