back.v

来自「FPGA设计中乒乓设计的源代码」· Verilog 代码 · 共 65 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:30:21 12/26/07
// Design Name:    
// Module Name:    back
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module back(clk_5m,rst, nd_a, nd_b, indata_a, indata_b, out, rdy);
    input clk_5m;
	 input rst;
    input nd_a;
    input nd_b;
    input [15:0] indata_a;
    input [15:0] indata_b;
    output [15:0]  out;
    output rdy;

    reg [15:0] out;
	 reg rdy;

	 reg state;

	 always @(posedge rst or posedge clk_5m)
	 begin
	  if(rst)
	    begin
		  rdy<=0;
		  state<=0;
		 end
	  else
	   case(state)
		1'b0:
		  if(nd_a==1)
		    begin
			  out<=indata_a;
			  rdy<=1;
			  state<=1;
			 end
		1'b1:
		  if(nd_b==1)
		    begin
			  out<=indata_b;
			  rdy<=1;
			  state<=0;
			 end
		default:rdy<=0; 
		endcase
	  end		     
		 

endmodule