📄 nvim_items.h
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nvi_byte_type fm_dacc_qaccum2;
nvi_byte_type gps_dacc_qaccum2;
nvi_byte_type cdma_dacc_qaccum3;
nvi_byte_type pcs_dacc_qaccum3;
nvi_byte_type fm_dacc_qaccum3;
nvi_byte_type gps_dacc_qaccum3;
nvi_byte_type cdma_dacc_qaccum4;
nvi_byte_type pcs_dacc_qaccum4;
nvi_byte_type fm_dacc_qaccum4;
nvi_byte_type gps_dacc_qaccum4;
nvi_byte_type cdma_dacc_gain_mult;
nvi_byte_type pcs_dacc_gain_mult;
nvi_byte_type fm_dacc_gain_mult;
nvi_byte_type gps_dacc_gain_mult;
nvi_byte_type cdma_im2_i_value;
nvi_byte_type pcs_im2_i_value;
nvi_byte_type cdma_im2_q_value;
nvi_byte_type pcs_im2_q_value;
nvi_byte_type rtc_time_adjust;
nvi_int2_type fm_vga_gain_offset;
nvi_int2_type cdma_vga_gain_offset;
nvi_int2_type pcs_vga_gain_offset;
nvi_fm_vga_gain_offset_vs_freq_type fm_vga_gain_offset_vs_freq;
nvi_cdma_vga_gain_offset_vs_freq_type cdma_vga_gain_offset_vs_freq;
nvi_pcs_vga_gain_offset_vs_freq_type pcs_vga_gain_offset_vs_freq;
nvi_fm_vga_gain_offset_vs_temp_type fm_vga_gain_offset_vs_temp;
nvi_cdma_vga_gain_offset_vs_temp_type cdma_vga_gain_offset_vs_temp;
nvi_pcs_vga_gain_offset_vs_temp_type pcs_vga_gain_offset_vs_temp;
nvi_int32_type fm_mis_comp_a_offset;
nvi_int32_type digital_mis_comp_a_offset;
nvi_int32_type gps_mis_comp_a_offset;
nvi_int32_type fm_mis_comp_b_offset;
nvi_int32_type digital_mis_comp_b_offset;
nvi_int32_type gps_mis_comp_b_offset;
nvi_int1_type pcs_im_level3;
nvi_int1_type pcs_im_level4;
nvi_int1_type pcs_agc_value_3_min;
nvi_int1_type pcs_agc_value_4_min;
nvi_byte_type digital_pll_lock_timer;
nvi_int2_type cdma_tx_gain_atten_limit;
nvi_int2_type pcs_tx_gain_atten_limit;
nvi_int2_type amps_tx_gain_atten_limit;
nvi_int2_type gps_tx_gain_atten_limit;
nvi_byte_type cdma_im2_transconductor_value;
nvi_byte_type pcs_im2_transconductor_value;
nvi_byte_type fm_pa_mac_high;
nvi_int2_type cdma_dynamic_range;
nvi_int2_type cdma_min_rx_rssi;
nvi_word_type tx_warmup;
nvi_cdma_p1_rise_fall_off_type cdma_p1_rise_fall_off;
nvi_pcs_p1_rise_fall_off_type pcs_p1_rise_fall_off;
nvi_word_type pcs_lna_bypass_timer_0;
nvi_wcdma_rx_lin_type wcdma_rx_lin;
nvi_wcdma_rx_comp_vs_freq_type wcdma_rx_comp_vs_freq;
nvi_wcdma_rx_lin_vs_temp_type wcdma_rx_lin_vs_temp;
nvi_wcdma_rx_slp_vs_temp_type wcdma_rx_slp_vs_temp;
nvi_uint8_type wcdma_lna_range_pol;
nvi_int16_type wcdma_lna_range_rise;
nvi_int16_type wcdma_lna_range_fall;
nvi_int16_type wcdma_im_level;
nvi_uint8_type wcdma_nonbypass_timer;
nvi_uint16_type wcdma_bypass_timer;
nvi_int16_type wcdma_lna_range_offset;
nvi_wcdma_lna_offset_vs_freq_type wcdma_lna_offset_vs_freq;
nvi_int16_type wcdma_rx_agc_min;
nvi_int16_type wcdma_rx_agc_max;
nvi_uint8_type wcdma_agc_phase_offset;
nvi_wcdma_tx_lin_master_0_type wcdma_tx_lin_master_0;
nvi_wcdma_tx_lin_master_1_type wcdma_tx_lin_master_1;
nvi_wcdma_tx_comp_vs_freq_0_type wcdma_tx_comp_vs_freq_0;
nvi_wcdma_tx_comp_vs_freq_1_type wcdma_tx_comp_vs_freq_1;
nvi_wcdma_tx_lin_vs_temp_0_type wcdma_tx_lin_vs_temp_0;
nvi_wcdma_tx_lin_vs_temp_1_type wcdma_tx_lin_vs_temp_1;
nvi_wcdma_tx_slp_vs_temp_0_type wcdma_tx_slp_vs_temp_0;
nvi_wcdma_tx_slp_vs_temp_1_type wcdma_tx_slp_vs_temp_1;
nvi_uint16_type wcdma_r1_rise;
nvi_uint16_type wcdma_r1_fall;
nvi_wcdma_tx_lim_vs_temp_type wcdma_tx_lim_vs_temp;
nvi_wcdma_tx_lim_vs_freq_type wcdma_tx_lim_vs_freq;
nvi_uint8_type wcdma_adj_factor;
nvi_wcdma_exp_hdet_vs_agc_type wcdma_exp_hdet_vs_agc;
nvi_uint8_type wcdma_hdet_off;
nvi_uint8_type wcdma_hdet_spn;
nvi_uint32_type wcdma_enc_btf;
nvi_int16_type wcdma_vga_gain_offset;
nvi_wcdma_vga_gain_offset_vs_freq_type wcdma_vga_gain_offset_vs_freq;
nvi_wcdma_vga_gain_offset_vs_temp_type wcdma_vga_gain_offset_vs_temp;
nvi_int16_type wcdma_lna_range_rise_2;
nvi_int16_type wcdma_lna_range_rise_3;
nvi_int16_type wcdma_lna_range_fall_2;
nvi_int16_type wcdma_lna_range_fall_3;
nvi_int16_type wcdma_im_level_2;
nvi_int16_type wcdma_im_level_3;
nvi_int16_type wcdma_lna_range_offset_2;
nvi_int16_type wcdma_lna_range_offset_3;
nvi_wcdma_lna_offset_vs_freq_2_type wcdma_lna_offset_vs_freq_2;
nvi_wcdma_lna_offset_vs_freq_3_type wcdma_lna_offset_vs_freq_3;
nvi_uint8_type wcdma_im2_i_value;
nvi_uint8_type wcdma_im2_q_value;
nvi_uint8_type wcdma_im2_transconductor_value;
nvi_int16_type wcdma_rx_agc_min_2;
nvi_int16_type wcdma_rx_agc_min_3;
nvi_wcdma_vbatt_type wcdma_vbatt;
nvi_wcdma_therm_type wcdma_therm;
nvi_int8_type wcdma_max_tx_power;
nvi_int16_type wcdma_out_of_service_thresh;
nvi_uint16_type wcdma_agc_pa_on_rise_delay;
nvi_uint16_type wcdma_agc_pa_on_fall_delay;
nvi_uint16_type wcdma_agc_tx_on_rise_delay;
nvi_uint16_type wcdma_agc_tx_on_fall_delay;
nvi_uint16_type wcdma_agc_update_tx_agc_time;
nvi_uint16_type trk_lo_adj_default;
nvi_uint16_type trk_lo_adj_slope_default;
nvi_uint16_type wcdma_pa_gain_up_time;
nvi_uint16_type wcdma_pa_gain_down_time;
nvi_uint8_type rfr_bb_filter;
nvi_uint8_type rfr_iq_line_resistor;
nvi_rfr_vco_coarse_tuning_1900_type rfr_vco_coarse_tuning_1900;
nvi_uint16_type wcdma_tx_rot_angle_pa_state_00;
nvi_uint16_type wcdma_tx_rot_angle_pa_state_01;
nvi_uint16_type wcdma_tx_rot_angle_pa_state_10;
nvi_uint16_type wcdma_tx_rot_angle_pa_state_11;
nvi_int16_type pa_compensate_up;
nvi_int16_type pa_compensate_down;
nvi_int2_type c1_cdma_lna_offset;
nvi_c1_cdma_lna_offset_vs_freq_type c1_cdma_lna_offset_vs_freq;
nvi_int2_type c1_pcs_lna_offset;
nvi_c1_pcs_lna_offset_vs_freq_type c1_pcs_lna_offset_vs_freq;
nvi_int2_type c1_cdma_lna_2_offset;
nvi_c1_cdma_lna_2_offset_vs_freq_type c1_cdma_lna_2_offset_vs_freq;
nvi_int2_type c1_pcs_lna_2_offset;
nvi_c1_pcs_lna_2_offset_vs_freq_type c1_pcs_lna_2_offset_vs_freq;
nvi_int2_type c1_cdma_lna_3_offset;
nvi_c1_cdma_lna_3_offset_vs_freq_type c1_cdma_lna_3_offset_vs_freq;
nvi_int2_type c1_pcs_lna_3_offset;
nvi_c1_pcs_lna_3_offset_vs_freq_type c1_pcs_lna_3_offset_vs_freq;
nvi_int2_type c1_cdma_lna_4_offset;
nvi_c1_cdma_lna_4_offset_vs_freq_type c1_cdma_lna_4_offset_vs_freq;
nvi_int2_type c1_pcs_lna_4_offset;
nvi_c1_pcs_lna_4_offset_vs_freq_type c1_pcs_lna_4_offset_vs_freq;
nvi_c1_cdma_p1_rise_fall_offset_type c1_cdma_p1_rise_fall_offset;
nvi_c1_pcs_p1_rise_fall_offset_type c1_pcs_p1_rise_fall_offset;
nvi_minmax_type c1_rx_agc_value_1_minmax;
nvi_minmax_type c1_rx_agc_value_2_minmax;
nvi_minmax_type c1_rx_agc_value_3_minmax;
nvi_minmax_type c1_rx_agc_value_4_minmax;
nvi_byte_type c0_rx_agc_vref_val;
nvi_byte_type c1_rx_agc_vref_val;
nvi_byte_type c0_grp_delay_adj;
nvi_byte_type c1_grp_delay_adj;
nvi_int2_type c1_cdma_vga_gain_offset;
nvi_c1_cdma_vga_gain_offset_vs_freq_type c1_cdma_vga_gain_offset_vs_freq;
nvi_c1_cdma_vga_gain_offset_vs_temp_type c1_cdma_vga_gain_offset_vs_temp;
nvi_int2_type c1_pcs_vga_gain_offset;
nvi_c1_pcs_vga_gain_offset_vs_freq_type c1_pcs_vga_gain_offset_vs_freq;
nvi_c1_pcs_vga_gain_offset_vs_temp_type c1_pcs_vga_gain_offset_vs_temp;
nvi_int4_type c1_digital_mis_comp_a_offset;
nvi_int4_type c1_gps_mis_comp_a_offset;
nvi_int4_type c1_digital_mis_comp_b_offset;
nvi_int4_type c1_gps_mis_comp_b_offset;
nvi_byte_type c1_cdma_dacc_iaccum0;
nvi_byte_type c1_pcs_dacc_iaccum0;
nvi_byte_type c1_gps_dacc_iaccum0;
nvi_byte_type c1_cdma_dacc_iaccum1;
nvi_byte_type c1_pcs_dacc_iaccum1;
nvi_byte_type c1_gps_dacc_iaccum1;
nvi_byte_type c1_cdma_dacc_iaccum2;
nvi_byte_type c1_pcs_dacc_iaccum2;
nvi_byte_type c1_gps_dacc_iaccum2;
nvi_byte_type c1_cdma_dacc_iaccum3;
nvi_byte_type c1_pcs_dacc_iaccum3;
nvi_byte_type c1_gps_dacc_iaccum3;
nvi_byte_type c1_cdma_dacc_iaccum4;
nvi_byte_type c1_pcs_dacc_iaccum4;
nvi_byte_type c1_gps_dacc_iaccum4;
nvi_byte_type c1_cdma_dacc_qaccum0;
nvi_byte_type c1_pcs_dacc_qaccum0;
nvi_byte_type c1_gps_dacc_qaccum0;
nvi_byte_type c1_cdma_dacc_qaccum1;
nvi_byte_type c1_pcs_dacc_qaccum1;
nvi_byte_type c1_gps_dacc_qaccum1;
nvi_byte_type c1_cdma_dacc_qaccum2;
nvi_byte_type c1_pcs_dacc_qaccum2;
nvi_byte_type c1_gps_dacc_qaccum2;
nvi_byte_type c1_cdma_dacc_qaccum3;
nvi_byte_type c1_pcs_dacc_qaccum3;
nvi_byte_type c1_gps_dacc_qaccum3;
nvi_byte_type c1_cdma_dacc_qaccum4;
nvi_byte_type c1_pcs_dacc_qaccum4;
nvi_byte_type c1_gps_dacc_qaccum4;
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