lpc236x.h

又一个arm上跑的实时内核的源码,gcc 编译

#define rAHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))

//-- System Controls and Status --

#define rSCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))

//-- MPMC(EMC) registers, note: all the external memory controller(EMC)
//-- registers are for LPC24xx only.

#define rSTATIC_MEM0_BASE                0x80000000
#define rSTATIC_MEM1_BASE                0x81000000
#define rSTATIC_MEM2_BASE                0x82000000
#define rSTATIC_MEM3_BASE                0x83000000

#define rDYNAMIC_MEM0_BASE                0xA0000000
#define rDYNAMIC_MEM1_BASE                0xB0000000
#define rDYNAMIC_MEM2_BASE                0xC0000000
#define rDYNAMIC_MEM3_BASE                0xD0000000

//-- External Memory Controller (EMC) --

#define EMC_BASE_ADDR                0xFFE08000

#define rEMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
#define rEMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
#define rEMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))

//-- Dynamic RAM access registers --

#define rEMC_DYN_CTRL     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
#define rEMC_DYN_RFSH     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
#define rEMC_DYN_RD_CFG   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
#define rEMC_DYN_RP       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
#define rEMC_DYN_RAS      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
#define rEMC_DYN_SREX     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
#define rEMC_DYN_APR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
#define rEMC_DYN_DAL      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
#define rEMC_DYN_WR       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
#define rEMC_DYN_RC       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
#define rEMC_DYN_RFC      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
#define rEMC_DYN_XSR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
#define rEMC_DYN_RRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
#define rEMC_DYN_MRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))

#define rEMC_DYN_CFG0     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
#define rEMC_DYN_RASCAS0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
#define rEMC_DYN_CFG1     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
#define rEMC_DYN_RASCAS1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
#define rEMC_DYN_CFG2     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
#define rEMC_DYN_RASCAS2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
#define rEMC_DYN_CFG3     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180))
#define rEMC_DYN_RASCAS3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184))

//-- static RAM access registers --

#define rEMC_STA_CFG0      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
#define rEMC_STA_WAITWEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
#define rEMC_STA_WAITOEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
#define rEMC_STA_WAITRD0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
#define rEMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
#define rEMC_STA_WAITWR0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
#define rEMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))

#define rEMC_STA_CFG1      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
#define rEMC_STA_WAITWEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
#define rEMC_STA_WAITOEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
#define rEMC_STA_WAITRD1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
#define rEMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
#define rEMC_STA_WAITWR1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
#define rEMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))

#define rEMC_STA_CFG2      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
#define rEMC_STA_WAITWEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
#define rEMC_STA_WAITOEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
#define rEMC_STA_WAITRD2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
#define rEMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
#define rEMC_STA_WAITWR2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
#define rEMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))

#define rEMC_STA_CFG3      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
#define rEMC_STA_WAITWEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
#define rEMC_STA_WAITOEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
#define rEMC_STA_WAITRD3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
#define rEMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
#define rEMC_STA_WAITWR3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
#define rEMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))

#define rEMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))

//-- Timer 0 --

#define TMR0_BASE_ADDR                0xE0004000

#define rT0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
#define rT0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
#define rT0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
#define rT0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
#define rT0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
#define rT0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
#define rT0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
#define rT0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
#define rT0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
#define rT0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
#define rT0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
#define rT0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
#define rT0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
#define rT0CR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
#define rT0CR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
#define rT0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
#define rT0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))

//-- Timer 1 --

#define TMR1_BASE_ADDR                0xE0008000

#define rT1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
#define rT1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
#define rT1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
#define rT1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
#define rT1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
#define rT1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
#define rT1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
#define rT1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
#define rT1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
#define rT1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
#define rT1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
#define rT1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
#define rT1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
#define rT1CR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
#define rT1CR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
#define rT1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
#define rT1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))

//-- Timer 2 --

#define TMR2_BASE_ADDR                0xE0070000

#define rT2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
#define rT2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
#define rT2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
#define rT2PR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
#define rT2PC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
#define rT2MCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
#define rT2MR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
#define rT2MR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
#define rT2MR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
#define rT2MR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
#define rT2CCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
#define rT2CR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
#define rT2CR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
#define rT2CR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
#define rT2CR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
#define rT2EMR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
#define rT2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))

//-- Timer 3 --

#define TMR3_BASE_ADDR                0xE0074000

#define rT3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
#define rT3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
#define rT3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
#define rT3PR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
#define rT3PC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
#define rT3MCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
#define rT3MR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
#define rT3MR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
#define rT3MR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
#define rT3MR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
#define rT3CCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
#define rT3CR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
#define rT3CR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
#define rT3CR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
#define rT3CR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
#define rT3EMR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
#define rT3CTCR         (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))


//-- Pulse Width Modulator (PWM) --

#define PWM0_BASE_ADDR                0xE0014000

#define rPWM0IR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
#define rPWM0TCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
#define rPWM0TC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
#define rPWM0PR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
#define rPWM0PC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
#define rPWM0MCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
#define rPWM0MR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
#define rPWM0MR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
#define rPWM0MR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
#define rPWM0MR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
#define rPWM0CCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
#define rPWM0CR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
#define rPWM0CR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
#define rPWM0CR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
#define rPWM0CR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
#define rPWM0EMR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
#define rPWM0MR4         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
#define rPWM0MR5         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
#define rPWM0MR6         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
#define rPWM0PCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
#define rPWM0LER         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
#define rPWM0CTCR        (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))

#define PWM1_BASE_ADDR                0xE0018000

#define rPWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
#define rPWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
#define rPWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
#define rPWM1PR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
#define rPWM1PC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
#define rPWM1MCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
#define rPWM1MR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
#define rPWM1MR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
#define rPWM1MR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))