📄 hardware.lst
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// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
00008E1A 40 92 r1=0x0000; // 24MHz, Fcpu=Fosc
00008E1B 19 D3 13 70 [P_SystemClock]=r1 // Frequency 20MHz
00008E1D 70 92 r1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008E1E 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
00008E20 09 93 00 FD r1 = 0xfd00 // 16K
00008E22 19 D3 0A 70 [P_TimerA_Data] = r1
00008E24 09 93 A8 00 r1 = 0x00A8 // Set the DAC Ctrl
00008E26 19 D3 2A 70 [P_DAC_Ctrl] = r1
00008E28 09 93 FF FF r1 = 0xffff
00008E2A 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00008E2C 40 92 r1 =0x0000 //
// r1 = [R_InterruptStatus] //
00008E2D 11 93 2D 70 r1 = [P_INT_Mask]
00008E2F 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
00008E31 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008E33 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008E34 40 92 r1 = 0x0000 // 24MHz Fosc
00008E35 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
00008E37 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008E38 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
00008E3A 09 93 ED FC r1 = 0xfced // 15.625K
00008E3C 19 D3 0A 70 [P_TimerA_Data]=r1
00008E3E 09 93 A8 00 r1 = 0x00A8 //
00008E40 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
00008E42 09 93 FF FF r1 = 0xffff
00008E44 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// R1 = [R_InterruptStatus] //
00008E46 11 93 2D 70 r1 = [P_INT_Mask]
00008E48 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
// [R_InterruptStatus] = r1 //
00008E4A 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008E4C 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
00008E4D 60 92 r1=0x0020;
00008E4E 19 D3 13 70 [P_SystemClock]=r1
00008E50 09 93 A8 00 r1 = 0x00A8; //
00008E52 19 D3 2A 70 [P_DAC_Ctrl]= r1
00008E54 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008E55 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00008E57 09 93 00 FE r1 = 0xfe00; // 24K
00008E59 19 D3 0A 70 [P_TimerA_Data] = r1;
00008E5B 09 93 FF FF r1 = 0xffff
00008E5D 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
00008E5F 11 93 2D 70 r1 = [P_INT_Mask]
00008E61 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
00008E63 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008E65 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00008E66 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00008E67 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
00008E69 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008E6A 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
00008E6C 40 92 r1 = 0x0000 // Fosc/2
00008E6D 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
00008E6F 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
00008E71 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
00008E73 09 93 FF FF r1 = 0xffff
00008E75 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00008E77 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00008E78 46 92 r1 = 0x0006
00008E79 19 D3 2A 70 [P_DAC_Ctrl] = r1
00008E7B 09 93 00 FE r1 = 0xFE00
00008E7D 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00008E7F 11 93 2D 70 r1 = [P_INT_Mask]
00008E81 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
00008E83 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008E85 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00008E86 09 93 A8 00 r1 = 0x00A8
00008E88 19 D3 2A 70 [P_DAC_Ctrl] = r1
00008E8A 09 93 00 FE r1 = 0xFE00
00008E8C 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00008E8E 11 93 2D 70 r1 = [P_INT_Mask]
00008E90 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
00008E92 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008E94 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
00008E95 09 93 A8 00 r1 = 0x00A8
00008E97 19 D3 2A 70 [P_DAC_Ctrl] = r1
00008E99 09 93 9A FD r1 = 0xFD9A
00008E9B 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00008E9D 11 93 2D 70 r1 = [P_INT_Mask]
00008E9F 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
00008EA1 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008EA3 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
00008EA4 09 93 A8 00 r1 = 0x00A8
00008EA6 19 D3 2A 70 [P_DAC_Ctrl] = r1
00008EA8 09 93 00 FD r1 = 0xFD00
00008EAA 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00008EAC 11 93 2D 70 r1 = [P_INT_Mask]
// r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
00008EAE 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008EB0 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
00008EB1 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00008EB2 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
00008EB4 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008EB5 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00008EB7 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
00008EB9 19 D3 0A 70 [P_TimerA_Data] = r1;
00008EBB 75 92 r1 = 0x0035; // ADINI should be open (107)
00008EBC 19 D3 15 70 [P_ADC_Ctrl] = r1;
00008EBE 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
00008EC0 19 D3 2A 70 [P_DAC_Ctrl] = r1;
00008EC2 09 93 FF FF r1 = 0xffff;
00008EC4 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
00008EC6 11 93 2D 70 r1 = [P_INT_Mask]
00008EC8 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
00008ECA 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008ECC 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
00008ECD 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
00008ECE 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
00008ED0 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
00008ED2 19 D3 0A 70 [P_TimerA_Data] = r1
00008ED4 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
00008ED5 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
00008ED6 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
00008ED8 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
00008EDA 19 D3 0A 70 [P_TimerA_Data] = r1;
00008EDC 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
00008EDD 90 D4 push r1,r2 to [sp]
00008EDE 11 93 17 70 r1=[P_DAC1]
00008EE0 09 B3 C0 FF r1 &= ~0x003f
00008EE2 09 43 00 80 cmp r1,0x8000
00008EE4 0E 0E jb L_RU_NormalUp
00008EE5 19 5E je L_RU_End
L_RU_DownLoop:
00008EE6 40 F0 49 8F call F_Delay
00008EE8 41 94 r2 = 0x0001
00008EE9 1A D5 12 70 [P_Watchdog_Clear] = r2
00008EEB 09 23 40 00 r1 -= 0x40
00008EED 19 D3 17 70 [P_DAC1] = r1
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