clock.hif

来自「数字电子钟的Verilog HDL语言描述。」· HIF 代码 · 共 55 行

Version 6.0 Build 178 04/27/2006 SJ Full Version
36
1829
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
clock
# storage
db|clock.(0).cnf
db|clock.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock.v
f9e197a418e0ce8496b65b6dbe6dbb
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
countful
49999999
PARAMETER_DEC
DEF
counterfull_1k
49999
PARAMETER_DEC
DEF
}
# hierarchies {
|
}
# end
# complete