clock.map.summary

来自「数字电子钟的Verilog HDL语言描述。」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Thu Mar 05 19:27:55 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Total logic elements : 166
Total pins : 14
Total virtual pins : 0
UFM blocks : 0