clock.tan.summary

数字电子钟的Verilog HDL语言描述。

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.083 ns
From           : led_buf[1]
To             : out_data[2]
From Clock     : clk_100M
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk_100M'
Slack          : N/A
Required Time  : None
Actual Time    : 73.64 MHz ( period = 13.580 ns )
From           : count1[16]
To             : clk_1k
From Clock     : clk_100M
To Clock       : clk_100M
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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