📄 jishu.vht
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "03/13/2009 20:26:40"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : JISHU
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE JISHU_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT A_name : STRING (1 TO 1) := "A";
CONSTANT B_name : STRING (1 TO 1) := "B";
CONSTANT C_name : STRING (1 TO 1) := "C";
CONSTANT CO0_name : STRING (1 TO 3) := "CO0";
CONSTANT CO1_name : STRING (1 TO 3) := "CO1";
CONSTANT CO2_name : STRING (1 TO 3) := "CO2";
CONSTANT CO3_name : STRING (1 TO 3) := "CO3";
CONSTANT D_name : STRING (1 TO 1) := "D";
-- n(outputs)
CONSTANT o_num : INTEGER := 8;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END JISHU_vhd_tb_types;
PACKAGE BODY JISHU_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END JISHU_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.JISHU_vhd_tb_types.ALL;
ENTITY JISHU_vhd_sample_tst IS
PORT (
clk : IN STD_LOGIC;
sampler : OUT sample_type
);
END JISHU_vhd_sample_tst;
ARCHITECTURE sample_arch OF JISHU_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( clk )
BEGIN
IF (NOW > 0 ps) AND (NOW < 100000000 ps) THEN
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.JISHU_vhd_tb_types.ALL;
ENTITY JISHU_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CO0 : IN STD_LOGIC;
CO1 : IN STD_LOGIC;
CO2 : IN STD_LOGIC;
CO3 : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sampler : IN sample_type
);
END JISHU_vhd_check_tst;
ARCHITECTURE ovec_arch OF JISHU_vhd_check_tst IS
SIGNAL A_expected,A_expected_prev,A_prev : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL B_expected,B_expected_prev,B_prev : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C_expected,C_expected_prev,C_prev : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CO0_expected,CO0_expected_prev,CO0_prev : STD_LOGIC;
SIGNAL CO1_expected,CO1_expected_prev,CO1_prev : STD_LOGIC;
SIGNAL CO2_expected,CO2_expected_prev,CO2_prev : STD_LOGIC;
SIGNAL CO3_expected,CO3_expected_prev,CO3_prev : STD_LOGIC;
SIGNAL D_expected,D_expected_prev,D_prev : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
A_expected_prev <= A_expected;
B_expected_prev <= B_expected;
C_expected_prev <= C_expected;
CO0_expected_prev <= CO0_expected;
CO1_expected_prev <= CO1_expected;
CO2_expected_prev <= CO2_expected;
CO3_expected_prev <= CO3_expected;
D_expected_prev <= D_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
A_prev <= A;
B_prev <= B;
C_prev <= C;
CO0_prev <= CO0;
CO1_prev <= CO1;
CO2_prev <= CO2;
CO3_prev <= CO3;
D_prev <= D;
END PROCESS t_prcs_update_o_real_hist;
-- expected A[3]
t_prcs_A_3: PROCESS
BEGIN
A_expected(3) <= '0';
WAIT FOR 157927 ps;
FOR i IN 1 TO 499
LOOP
A_expected(3) <= '1';
WAIT FOR 40000 ps;
A_expected(3) <= '0';
WAIT FOR 160000 ps;
END LOOP;
A_expected(3) <= '1';
WAIT FOR 40000 ps;
A_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_A_3;
-- expected A[2]
t_prcs_A_2: PROCESS
BEGIN
A_expected(2) <= '0';
WAIT FOR 77977 ps;
FOR i IN 1 TO 499
LOOP
A_expected(2) <= '1';
WAIT FOR 80000 ps;
A_expected(2) <= '0';
WAIT FOR 120000 ps;
END LOOP;
A_expected(2) <= '1';
WAIT FOR 80000 ps;
A_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_A_2;
-- expected A[1]
t_prcs_A_1: PROCESS
BEGIN
A_expected(1) <= '0';
WAIT FOR 38336 ps;
FOR i IN 1 TO 499
LOOP
A_expected(1) <= '1';
WAIT FOR 40000 ps;
A_expected(1) <= '0';
WAIT FOR 40000 ps;
A_expected(1) <= '1';
WAIT FOR 40000 ps;
A_expected(1) <= '0';
WAIT FOR 80000 ps;
END LOOP;
A_expected(1) <= '1';
WAIT FOR 40000 ps;
A_expected(1) <= '0';
WAIT FOR 40000 ps;
A_expected(1) <= '1';
WAIT FOR 40000 ps;
A_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_A_1;
-- expected A[0]
t_prcs_A_0: PROCESS
BEGIN
A_expected(0) <= '0';
WAIT FOR 18037 ps;
FOR i IN 1 TO 2499
LOOP
A_expected(0) <= '1';
WAIT FOR 20000 ps;
A_expected(0) <= '0';
WAIT FOR 20000 ps;
END LOOP;
A_expected(0) <= '1';
WAIT FOR 20000 ps;
A_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_A_0;
-- expected CO0
t_prcs_CO0: PROCESS
BEGIN
CO0_expected <= '0';
WAIT FOR 179470 ps;
FOR i IN 1 TO 499
LOOP
CO0_expected <= '1';
WAIT FOR 20000 ps;
CO0_expected <= '0';
WAIT FOR 180000 ps;
END LOOP;
CO0_expected <= '1';
WAIT FOR 20000 ps;
CO0_expected <= '0';
WAIT;
END PROCESS t_prcs_CO0;
-- expected B[3]
t_prcs_B_3: PROCESS
BEGIN
B_expected(3) <= '0';
WAIT FOR 1598013 ps;
FOR i IN 1 TO 49
LOOP
B_expected(3) <= '1';
WAIT FOR 400000 ps;
B_expected(3) <= '0';
WAIT FOR 1600000 ps;
END LOOP;
B_expected(3) <= '1';
WAIT FOR 400000 ps;
B_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_B_3;
-- expected B[2]
t_prcs_B_2: PROCESS
BEGIN
B_expected(2) <= '0';
WAIT FOR 797569 ps;
FOR i IN 1 TO 49
LOOP
B_expected(2) <= '1';
WAIT FOR 800000 ps;
B_expected(2) <= '0';
WAIT FOR 1200000 ps;
END LOOP;
B_expected(2) <= '1';
WAIT FOR 800000 ps;
B_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_B_2;
-- expected B[1]
t_prcs_B_1: PROCESS
BEGIN
B_expected(1) <= '0';
WAIT FOR 398039 ps;
FOR i IN 1 TO 49
LOOP
B_expected(1) <= '1';
WAIT FOR 400000 ps;
B_expected(1) <= '0';
WAIT FOR 400000 ps;
B_expected(1) <= '1';
WAIT FOR 400000 ps;
B_expected(1) <= '0';
WAIT FOR 800000 ps;
END LOOP;
B_expected(1) <= '1';
WAIT FOR 400000 ps;
B_expected(1) <= '0';
WAIT FOR 400000 ps;
B_expected(1) <= '1';
WAIT FOR 400000 ps;
B_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_B_1;
-- expected B[0]
t_prcs_B_0: PROCESS
BEGIN
B_expected(0) <= '0';
WAIT FOR 197906 ps;
FOR i IN 1 TO 249
LOOP
B_expected(0) <= '1';
WAIT FOR 200000 ps;
B_expected(0) <= '0';
WAIT FOR 200000 ps;
END LOOP;
B_expected(0) <= '1';
WAIT FOR 200000 ps;
B_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_B_0;
-- expected CO1
t_prcs_CO1: PROCESS
BEGIN
CO1_expected <= '0';
WAIT FOR 1598609 ps;
FOR i IN 1 TO 49
LOOP
CO1_expected <= '1';
WAIT FOR 392 ps;
CO1_expected <= '0';
WAIT FOR 359796 ps;
CO1_expected <= '1';
WAIT FOR 568 ps;
CO1_expected <= '0';
WAIT FOR 20000 ps;
CO1_expected <= '1';
WAIT FOR 19244 ps;
CO1_expected <= '0';
WAIT FOR 1600000 ps;
END LOOP;
CO1_expected <= '1';
WAIT FOR 392 ps;
CO1_expected <= '0';
WAIT FOR 359796 ps;
CO1_expected <= '1';
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