jishu.tan.qmsg

eda的第六章课后习题答案,是个文件包

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register 74160:inst9\|6 register 74160:inst6\|9 290.11 MHz 3.447 ns Internal " "Info: Clock \"clk\" has Internal fmax of 290.11 MHz between source register \"74160:inst9\|6\" and destination register \"74160:inst6\|9\" (period= 3.447 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.183 ns + Longest register register " "Info: + Longest register to register delay is 3.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst9\|6 1 REG LCFF_X21_Y10_N5 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9\|6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74160:inst9|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.614 ns) 1.412 ns 74160:inst3\|45 2 COMB LCCOMB_X21_Y10_N0 11 " "Info: 2: + IC(0.798 ns) + CELL(0.614 ns) = 1.412 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 11; COMB Node = '74160:inst3\|45'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.412 ns" { 74160:inst9|6 74160:inst3|45 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.370 ns) 2.506 ns 74160:inst6\|45~12 3 COMB LCCOMB_X21_Y10_N22 1 " "Info: 3: + IC(0.724 ns) + CELL(0.370 ns) = 2.506 ns; Loc. = LCCOMB_X21_Y10_N22; Fanout = 1; COMB Node = '74160:inst6\|45~12'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { 74160:inst3|45 74160:inst6|45~12 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 3.075 ns 74160:inst6\|13~131 4 COMB LCCOMB_X21_Y10_N18 1 " "Info: 4: + IC(0.363 ns) + CELL(0.206 ns) = 3.075 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = '74160:inst6\|13~131'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { 74160:inst6|45~12 74160:inst6|13~131 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 912 976 824 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.183 ns 74160:inst6\|9 5 REG LCFF_X21_Y10_N19 4 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.183 ns; Loc. = LCFF_X21_Y10_N19; Fanout = 4; REG Node = '74160:inst6\|9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { 74160:inst6|13~131 74160:inst6|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.298 ns ( 40.78 % ) " "Info: Total cell delay = 1.298 ns ( 40.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.885 ns ( 59.22 % ) " "Info: Total interconnect delay = 1.885 ns ( 59.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.183 ns" { 74160:inst9|6 74160:inst3|45 74160:inst6|45~12 74160:inst6|13~131 74160:inst6|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.183 ns" { 74160:inst9|6 {} 74160:inst3|45 {} 74160:inst6|45~12 {} 74160:inst6|13~131 {} 74160:inst6|9 {} } { 0.000ns 0.798ns 0.724ns 0.363ns 0.000ns } { 0.000ns 0.614ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.758 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 2.758 ns 74160:inst6\|9 3 REG LCFF_X21_Y10_N19 4 " "Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N19; Fanout = 4; REG Node = '74160:inst6\|9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { clk~clkctrl 74160:inst6|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.03 % ) " "Info: Total cell delay = 1.766 ns ( 64.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns ( 35.97 % ) " "Info: Total interconnect delay = 0.992 ns ( 35.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst6|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst6|9 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.758 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 2.758 ns 74160:inst9\|6 3 REG LCFF_X21_Y10_N5 9 " "Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9\|6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.03 % ) " "Info: Total cell delay = 1.766 ns ( 64.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns ( 35.97 % ) " "Info: Total interconnect delay = 0.992 ns ( 35.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst9|6 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst6|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst6|9 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst9|6 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.183 ns" { 74160:inst9|6 74160:inst3|45 74160:inst6|45~12 74160:inst6|13~131 74160:inst6|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.183 ns" { 74160:inst9|6 {} 74160:inst3|45 {} 74160:inst6|45~12 {} 74160:inst6|13~131 {} 74160:inst6|9 {} } { 0.000ns 0.798ns 0.724ns 0.363ns 0.000ns } { 0.000ns 0.614ns 0.370ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst6|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst6|9 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst9|6 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk CO3 74160:inst9\|6 12.237 ns register " "Info: tco from clock \"clk\" to destination pin \"CO3\" through register \"74160:inst9\|6\" is 12.237 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.758 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 488 144 312 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 2.758 ns 74160:inst9\|6 3 REG LCFF_X21_Y10_N5 9 " "Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9\|6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.03 % ) " "Info: Total cell delay = 1.766 ns ( 64.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns ( 35.97 % ) " "Info: Total interconnect delay = 0.992 ns ( 35.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst9|6 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.175 ns + Longest register pin " "Info: + Longest register to pin delay is 9.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst9\|6 1 REG LCFF_X21_Y10_N5 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9\|6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74160:inst9|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.614 ns) 1.412 ns 74160:inst3\|45 2 COMB LCCOMB_X21_Y10_N0 11 " "Info: 2: + IC(0.798 ns) + CELL(0.614 ns) = 1.412 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 11; COMB Node = '74160:inst3\|45'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.412 ns" { 74160:inst9|6 74160:inst3|45 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.436 ns) + CELL(0.370 ns) 3.218 ns 74160:inst6\|45 3 COMB LCCOMB_X20_Y11_N18 1 " "Info: 3: + IC(1.436 ns) + CELL(0.370 ns) = 3.218 ns; Loc. = LCCOMB_X20_Y11_N18; Fanout = 1; COMB Node = '74160:inst6\|45'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.806 ns" { 74160:inst3|45 74160:inst6|45 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.711 ns) + CELL(3.246 ns) 9.175 ns CO3 4 PIN PIN_142 0 " "Info: 4: + IC(2.711 ns) + CELL(3.246 ns) = 9.175 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'CO3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.957 ns" { 74160:inst6|45 CO3 } "NODE_NAME" } } { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 1464 464 640 1480 "CO3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.230 ns ( 46.10 % ) " "Info: Total cell delay = 4.230 ns ( 46.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.945 ns ( 53.90 % ) " "Info: Total interconnect delay = 4.945 ns ( 53.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.175 ns" { 74160:inst9|6 74160:inst3|45 74160:inst6|45 CO3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.175 ns" { 74160:inst9|6 {} 74160:inst3|45 {} 74160:inst6|45 {} CO3 {} } { 0.000ns 0.798ns 1.436ns 2.711ns } { 0.000ns 0.614ns 0.370ns 3.246ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { clk clk~clkctrl 74160:inst9|6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { clk {} clk~combout {} clk~clkctrl {} 74160:inst9|6 {} } { 0.000ns 0.000ns 0.143ns 0.849ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.175 ns" { 74160:inst9|6 74160:inst3|45 74160:inst6|45 CO3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.175 ns" { 74160:inst9|6 {} 74160:inst3|45 {} 74160:inst6|45 {} CO3 {} } { 0.000ns 0.798ns 1.436ns 2.711ns } { 0.000ns 0.614ns 0.370ns 3.246ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 20:22:04 2009 " "Info: Processing ended: Fri Mar 13 20:22:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}