jishu.map.qmsg

eda的第六章课后习题答案,是个文件包

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 13 20:21:38 2009 " "Info: Processing started: Fri Mar 13 20:21:38 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JISHU -c JISHU " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JISHU -c JISHU" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JISHU.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file JISHU.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 JISHU " "Info: Found entity 1: JISHU" {  } { { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JISHU " "Info: Elaborating entity \"JISHU\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74160 " "Info: Found entity 1: 74160" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74160 74160:inst9 " "Info: Elaborating entity \"74160\" for hierarchy \"74160:inst9\"" {  } { { "JISHU.bdf" "inst9" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 336 336 456 520 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "74160 " "Warning: Processing legacy GDF or BDF entity \"74160\" with Max+Plus II bus and instance naming rules" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WGDFX_MIXED_DESIGN_FILE_NAMING" "" "Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74160:inst9 " "Info: Elaborated megafunction instantiation \"74160:inst9\"" {  } { { "JISHU.bdf" "" { Schematic "G:/EDA/JISHU/JISHU.bdf" { { 336 336 456 520 "inst9" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "46 " "Info: Implemented 46 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 20:21:42 2009 " "Info: Processing ended: Fri Mar 13 20:21:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}