jishu.tan.rpt

eda的第六章课后习题答案,是个文件包

; N/A   ; None         ; 12.237 ns  ; 74160:inst9|6 ; CO3  ; clk        ;
; N/A   ; None         ; 11.873 ns  ; 74160:inst3|6 ; CO3  ; clk        ;
; N/A   ; None         ; 11.669 ns  ; 74160:inst9|9 ; CO3  ; clk        ;
; N/A   ; None         ; 11.551 ns  ; 74160:inst6|6 ; CO3  ; clk        ;
; N/A   ; None         ; 11.481 ns  ; 74160:inst3|9 ; CO3  ; clk        ;
; N/A   ; None         ; 11.149 ns  ; 74160:inst4|6 ; CO3  ; clk        ;
; N/A   ; None         ; 10.778 ns  ; 74160:inst4|9 ; CO3  ; clk        ;
; N/A   ; None         ; 10.711 ns  ; 74160:inst6|9 ; CO3  ; clk        ;
; N/A   ; None         ; 10.683 ns  ; 74160:inst9|6 ; CO2  ; clk        ;
; N/A   ; None         ; 10.319 ns  ; 74160:inst3|6 ; CO2  ; clk        ;
; N/A   ; None         ; 10.115 ns  ; 74160:inst9|9 ; CO2  ; clk        ;
; N/A   ; None         ; 9.927 ns   ; 74160:inst3|9 ; CO2  ; clk        ;
; N/A   ; None         ; 9.635 ns   ; 74160:inst9|9 ; CO0  ; clk        ;
; N/A   ; None         ; 9.470 ns   ; 74160:inst9|6 ; CO0  ; clk        ;
; N/A   ; None         ; 9.365 ns   ; 74160:inst9|6 ; CO1  ; clk        ;
; N/A   ; None         ; 9.296 ns   ; 74160:inst6|9 ; D[3] ; clk        ;
; N/A   ; None         ; 9.287 ns   ; 74160:inst6|7 ; D[1] ; clk        ;
; N/A   ; None         ; 9.285 ns   ; 74160:inst4|9 ; C[3] ; clk        ;
; N/A   ; None         ; 9.001 ns   ; 74160:inst3|6 ; CO1  ; clk        ;
; N/A   ; None         ; 8.954 ns   ; 74160:inst4|9 ; CO2  ; clk        ;
; N/A   ; None         ; 8.850 ns   ; 74160:inst4|8 ; C[2] ; clk        ;
; N/A   ; None         ; 8.841 ns   ; 74160:inst6|6 ; D[0] ; clk        ;
; N/A   ; None         ; 8.797 ns   ; 74160:inst9|9 ; CO1  ; clk        ;
; N/A   ; None         ; 8.609 ns   ; 74160:inst3|9 ; CO1  ; clk        ;
; N/A   ; None         ; 8.336 ns   ; 74160:inst9|7 ; A[1] ; clk        ;
; N/A   ; None         ; 8.156 ns   ; 74160:inst4|6 ; CO2  ; clk        ;
; N/A   ; None         ; 8.059 ns   ; 74160:inst6|8 ; D[2] ; clk        ;
; N/A   ; None         ; 8.039 ns   ; 74160:inst3|7 ; B[1] ; clk        ;
; N/A   ; None         ; 8.037 ns   ; 74160:inst9|6 ; A[0] ; clk        ;
; N/A   ; None         ; 8.013 ns   ; 74160:inst3|9 ; B[3] ; clk        ;
; N/A   ; None         ; 7.977 ns   ; 74160:inst9|8 ; A[2] ; clk        ;
; N/A   ; None         ; 7.927 ns   ; 74160:inst9|9 ; A[3] ; clk        ;
; N/A   ; None         ; 7.906 ns   ; 74160:inst3|6 ; B[0] ; clk        ;
; N/A   ; None         ; 7.700 ns   ; 74160:inst4|7 ; C[1] ; clk        ;
; N/A   ; None         ; 7.569 ns   ; 74160:inst3|8 ; B[2] ; clk        ;
; N/A   ; None         ; 7.299 ns   ; 74160:inst4|6 ; C[0] ; clk        ;
+-------+--------------+------------+---------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Mar 13 20:22:01 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off JISHU -c JISHU --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 290.11 MHz between source register "74160:inst9|6" and destination register "74160:inst6|9" (period= 3.447 ns)
    Info: + Longest register to register delay is 3.183 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9|6'
        Info: 2: + IC(0.798 ns) + CELL(0.614 ns) = 1.412 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 11; COMB Node = '74160:inst3|45'
        Info: 3: + IC(0.724 ns) + CELL(0.370 ns) = 2.506 ns; Loc. = LCCOMB_X21_Y10_N22; Fanout = 1; COMB Node = '74160:inst6|45~12'
        Info: 4: + IC(0.363 ns) + CELL(0.206 ns) = 3.075 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = '74160:inst6|13~131'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.183 ns; Loc. = LCFF_X21_Y10_N19; Fanout = 4; REG Node = '74160:inst6|9'
        Info: Total cell delay = 1.298 ns ( 40.78 % )
        Info: Total interconnect delay = 1.885 ns ( 59.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.758 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N19; Fanout = 4; REG Node = '74160:inst6|9'
            Info: Total cell delay = 1.766 ns ( 64.03 % )
            Info: Total interconnect delay = 0.992 ns ( 35.97 % )
        Info: - Longest clock path from clock "clk" to source register is 2.758 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9|6'
            Info: Total cell delay = 1.766 ns ( 64.03 % )
            Info: Total interconnect delay = 0.992 ns ( 35.97 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "CO3" through register "74160:inst9|6" is 12.237 ns
    Info: + Longest clock path from clock "clk" to source register is 2.758 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9|6'
        Info: Total cell delay = 1.766 ns ( 64.03 % )
        Info: Total interconnect delay = 0.992 ns ( 35.97 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 9.175 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 9; REG Node = '74160:inst9|6'
        Info: 2: + IC(0.798 ns) + CELL(0.614 ns) = 1.412 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 11; COMB Node = '74160:inst3|45'
        Info: 3: + IC(1.436 ns) + CELL(0.370 ns) = 3.218 ns; Loc. = LCCOMB_X20_Y11_N18; Fanout = 1; COMB Node = '74160:inst6|45'
        Info: 4: + IC(2.711 ns) + CELL(3.246 ns) = 9.175 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'CO3'
        Info: Total cell delay = 4.230 ns ( 46.10 % )
        Info: Total interconnect delay = 4.945 ns ( 53.90 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Fri Mar 13 20:22:04 2009
    Info: Elapsed time: 00:00:03