📄 prev_cmp_jishixianshi.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 14 09:01:44 2009 " "Info: Processing started: Sat Mar 14 09:01:44 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JISHIXIANSHI -c JISHIXIANSHI " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JISHIXIANSHI -c JISHIXIANSHI" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JISHIXIANSHI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file JISHIXIANSHI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 JISHIXIANSHI-one " "Info: Found design unit 1: JISHIXIANSHI-one" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 13 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 JISHIXIANSHI " "Info: Found entity 1: JISHIXIANSHI" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JISHU.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file JISHU.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 JISHU " "Info: Found entity 1: JISHU" { } { { "JISHU.bdf" "" { Schematic "G:/EDA/JISHIXIANSHI/JISHU.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JISHIXIANSHI " "Info: Elaborating entity \"JISHIXIANSHI\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "clk1 JISHIXIANSHI.vhd(37) " "Warning (10036): Verilog HDL or VHDL warning at JISHIXIANSHI.vhd(37): object \"clk1\" assigned a value but never read" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 37 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_1 JISHIXIANSHI.vhd(67) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(67): signal \"CNT10_1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 67 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_2 JISHIXIANSHI.vhd(68) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(68): signal \"CNT10_2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 68 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_3 JISHIXIANSHI.vhd(69) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(69): signal \"CNT10_3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 69 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_4 JISHIXIANSHI.vhd(70) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(70): signal \"CNT10_4\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 70 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "clk_counter\[1\] JISHIXIANSHI.vhd(44) " "Error (10028): Can't resolve multiple constant drivers for net \"clk_counter\[1\]\" at JISHIXIANSHI.vhd(44)" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 44 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "JISHIXIANSHI.vhd(48) " "Error (10029): Constant driver at JISHIXIANSHI.vhd(48)" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 48 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "clk_counter\[0\] JISHIXIANSHI.vhd(44) " "Error (10028): Can't resolve multiple constant drivers for net \"clk_counter\[0\]\" at JISHIXIANSHI.vhd(44)" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 44 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" { } { } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 5 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Mar 14 09:01:47 2009 " "Error: Processing ended: Sat Mar 14 09:01:47 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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