jishixianshi.map.qmsg

eda的第六章课后习题答案,是个文件包

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 14 09:11:26 2009 " "Info: Processing started: Sat Mar 14 09:11:26 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JISHIXIANSHI -c JISHIXIANSHI " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JISHIXIANSHI -c JISHIXIANSHI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JISHIXIANSHI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file JISHIXIANSHI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 JISHIXIANSHI-one " "Info: Found design unit 1: JISHIXIANSHI-one" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 JISHIXIANSHI " "Info: Found entity 1: JISHIXIANSHI" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JISHU.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file JISHU.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 JISHU " "Info: Found entity 1: JISHU" {  } { { "JISHU.bdf" "" { Schematic "G:/EDA/JISHIXIANSHI/JISHU.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JISHIXIANSHI " "Info: Elaborating entity \"JISHIXIANSHI\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_1 JISHIXIANSHI.vhd(66) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(66): signal \"CNT10_1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 66 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_2 JISHIXIANSHI.vhd(67) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(67): signal \"CNT10_2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_3 JISHIXIANSHI.vhd(68) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(68): signal \"CNT10_3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CNT10_4 JISHIXIANSHI.vhd(69) " "Warning (10492): VHDL Process Statement warning at JISHIXIANSHI.vhd(69): signal \"CNT10_4\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 69 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JISHU JISHU:u1 " "Info: Elaborating entity \"JISHU\" for hierarchy \"JISHU:u1\"" {  } { { "JISHIXIANSHI.vhd" "u1" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74160 " "Info: Found entity 1: 74160" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74160 JISHU:u1\|74160:inst9 " "Info: Elaborating entity \"74160\" for hierarchy \"JISHU:u1\|74160:inst9\"" {  } { { "JISHU.bdf" "inst9" { Schematic "G:/EDA/JISHIXIANSHI/JISHU.bdf" { { 336 336 456 520 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "74160 " "Warning: Processing legacy GDF or BDF entity \"74160\" with Max+Plus II bus and instance naming rules" {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WGDFX_MIXED_DESIGN_FILE_NAMING" "" "Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." {  } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "JISHU:u1\|74160:inst9 " "Info: Elaborated megafunction instantiation \"JISHU:u1\|74160:inst9\"" {  } { { "JISHU.bdf" "" { Schematic "G:/EDA/JISHIXIANSHI/JISHU.bdf" { { 336 336 456 520 "inst9" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SG1\[5\] GND " "Warning (13410): Pin \"SG1\[5\]\" stuck at GND" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SG1\[6\] GND " "Warning (13410): Pin \"SG1\[6\]\" stuck at GND" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "EN " "Warning (15610): No output dependent on input pin \"EN\"" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RST " "Warning (15610): No output dependent on input pin \"RST\"" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "68 " "Info: Implemented 68 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 14 09:11:32 2009 " "Info: Processing ended: Sat Mar 14 09:11:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}