prev_cmp_jishixianshi.tan.qmsg

eda的第六章课后习题答案,是个文件包

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK0 register register CNT4\[0\] CNT4\[1\] 340.02 MHz Internal " "Info: Clock \"CLK0\" Internal fmax is restricted to 340.02 MHz between source register \"CNT4\[0\]\" and destination register \"CNT4\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.771 ns + Longest register register " "Info: + Longest register to register delay is 0.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4\[0\] 1 REG LCFF_X27_Y5_N11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y5_N11; Fanout = 6; REG Node = 'CNT4\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.206 ns) 0.663 ns CNT4\[1\]~20 2 COMB LCCOMB_X27_Y5_N2 1 " "Info: 2: + IC(0.457 ns) + CELL(0.206 ns) = 0.663 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 1; COMB Node = 'CNT4\[1\]~20'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.663 ns" { CNT4[0] CNT4[1]~20 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.771 ns CNT4\[1\] 3 REG LCFF_X27_Y5_N3 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.771 ns; Loc. = LCFF_X27_Y5_N3; Fanout = 5; REG Node = 'CNT4\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 40.73 % ) " "Info: Total cell delay = 0.314 ns ( 40.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.457 ns ( 59.27 % ) " "Info: Total interconnect delay = 0.457 ns ( 59.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.771 ns" { CNT4[0] CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.771 ns" { CNT4[0] {} CNT4[1]~20 {} CNT4[1] {} } { 0.000ns 0.457ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 destination 2.748 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK0\" to destination register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK0~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns CNT4\[1\] 3 REG LCFF_X27_Y5_N3 5 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N3; Fanout = 5; REG Node = 'CNT4\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 source 2.748 ns - Longest register " "Info: - Longest clock path from clock \"CLK0\" to source register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK0~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns CNT4\[0\] 3 REG LCFF_X27_Y5_N11 6 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N11; Fanout = 6; REG Node = 'CNT4\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.771 ns" { CNT4[0] CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.771 ns" { CNT4[0] {} CNT4[1]~20 {} CNT4[1] {} } { 0.000ns 0.457ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { CNT4[1] {} } {  } {  } "" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK0 BT\[0\] CNT4\[0\] 8.129 ns register " "Info: tco from clock \"CLK0\" to destination pin \"BT\[0\]\" through register \"CNT4\[0\]\" is 8.129 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 source 2.748 ns + Longest register " "Info: + Longest clock path from clock \"CLK0\" to source register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK0~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns CNT4\[0\] 3 REG LCFF_X27_Y5_N11 6 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N11; Fanout = 6; REG Node = 'CNT4\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.077 ns + Longest register pin " "Info: + Longest register to pin delay is 5.077 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4\[0\] 1 REG LCFF_X27_Y5_N11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y5_N11; Fanout = 6; REG Node = 'CNT4\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.489 ns) + CELL(0.651 ns) 1.140 ns Mux3~4 2 COMB LCCOMB_X27_Y5_N0 1 " "Info: 2: + IC(0.489 ns) + CELL(0.651 ns) = 1.140 ns; Loc. = LCCOMB_X27_Y5_N0; Fanout = 1; COMB Node = 'Mux3~4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.140 ns" { CNT4[0] Mux3~4 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(3.056 ns) 5.077 ns BT\[0\] 3 PIN PIN_87 0 " "Info: 3: + IC(0.881 ns) + CELL(3.056 ns) = 5.077 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'BT\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.937 ns" { Mux3~4 BT[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.707 ns ( 73.02 % ) " "Info: Total cell delay = 3.707 ns ( 73.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.370 ns ( 26.98 % ) " "Info: Total interconnect delay = 1.370 ns ( 26.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.077 ns" { CNT4[0] Mux3~4 BT[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.077 ns" { CNT4[0] {} Mux3~4 {} BT[0] {} } { 0.000ns 0.489ns 0.881ns } { 0.000ns 0.651ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.748 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.748 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.077 ns" { CNT4[0] Mux3~4 BT[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.077 ns" { CNT4[0] {} Mux3~4 {} BT[0] {} } { 0.000ns 0.489ns 0.881ns } { 0.000ns 0.651ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 23:00:46 2009 " "Info: Processing ended: Fri Mar 13 23:00:46 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}