jishixianshi.tan.qmsg

eda的第六章课后习题答案,是个文件包

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK0 SG\[4\] CNT4\[1\] 14.508 ns register " "Info: tco from clock \"CLK0\" to destination pin \"SG\[4\]\" through register \"CNT4\[1\]\" is 14.508 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 source 2.758 ns + Longest register " "Info: + Longest clock path from clock \"CLK0\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK0 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'CLK0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns CLK0~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'CLK0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.859 ns) + CELL(0.666 ns) 2.758 ns CNT4\[1\] 3 REG LCFF_X26_Y12_N19 11 " "Info: 3: + IC(0.859 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X26_Y12_N19; Fanout = 11; REG Node = 'CNT4\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.525 ns" { CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.67 % ) " "Info: Total cell delay = 1.756 ns ( 63.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 36.33 % ) " "Info: Total interconnect delay = 1.002 ns ( 36.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.446 ns + Longest register pin " "Info: + Longest register to pin delay is 11.446 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4\[1\] 1 REG LCFF_X26_Y12_N19 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y12_N19; Fanout = 11; REG Node = 'CNT4\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.950 ns) + CELL(0.206 ns) 2.156 ns Mux4~21 2 COMB LCCOMB_X27_Y12_N16 1 " "Info: 2: + IC(1.950 ns) + CELL(0.206 ns) = 2.156 ns; Loc. = LCCOMB_X27_Y12_N16; Fanout = 1; COMB Node = 'Mux4~21'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.156 ns" { CNT4[1] Mux4~21 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 3.203 ns Mux4~22 3 COMB LCCOMB_X27_Y12_N26 12 " "Info: 3: + IC(0.396 ns) + CELL(0.651 ns) = 3.203 ns; Loc. = LCCOMB_X27_Y12_N26; Fanout = 12; COMB Node = 'Mux4~22'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { Mux4~21 Mux4~22 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.370 ns) 5.262 ns Mux10~25 4 COMB LCCOMB_X27_Y5_N20 1 " "Info: 4: + IC(1.689 ns) + CELL(0.370 ns) = 5.262 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 1; COMB Node = 'Mux10~25'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.059 ns" { Mux4~22 Mux10~25 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.128 ns) + CELL(3.056 ns) 11.446 ns SG\[4\] 5 PIN PIN_25 0 " "Info: 5: + IC(3.128 ns) + CELL(3.056 ns) = 11.446 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'SG\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.184 ns" { Mux10~25 SG[4] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.283 ns ( 37.42 % ) " "Info: Total cell delay = 4.283 ns ( 37.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.163 ns ( 62.58 % ) " "Info: Total interconnect delay = 7.163 ns ( 62.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.446 ns" { CNT4[1] Mux4~21 Mux4~22 Mux10~25 SG[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.446 ns" { CNT4[1] {} Mux4~21 {} Mux4~22 {} Mux10~25 {} SG[4] {} } { 0.000ns 1.950ns 0.396ns 1.689ns 3.128ns } { 0.000ns 0.206ns 0.651ns 0.370ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.446 ns" { CNT4[1] Mux4~21 Mux4~22 Mux10~25 SG[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.446 ns" { CNT4[1] {} Mux4~21 {} Mux4~22 {} Mux10~25 {} SG[4] {} } { 0.000ns 1.950ns 0.396ns 1.689ns 3.128ns } { 0.000ns 0.206ns 0.651ns 0.370ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 14 09:11:53 2009 " "Info: Processing ended: Sat Mar 14 09:11:53 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}