📄 jishixianshi.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK0 " "Info: Assuming node \"CLK0\" is an undefined clock" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK0" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register JISHU:u1\|74160:inst9\|9 register JISHU:u1\|74160:inst4\|8 323.94 MHz 3.087 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 323.94 MHz between source register \"JISHU:u1\|74160:inst9\|9\" and destination register \"JISHU:u1\|74160:inst4\|8\" (period= 3.087 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.824 ns + Longest register register " "Info: + Longest register to register delay is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JISHU:u1\|74160:inst9\|9 1 REG LCFF_X26_Y12_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y12_N9; Fanout = 5; REG Node = 'JISHU:u1\|74160:inst9\|9'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { JISHU:u1|74160:inst9|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.589 ns) 1.037 ns JISHU:u1\|74160:inst3\|45~14 2 COMB LCCOMB_X26_Y12_N4 6 " "Info: 2: + IC(0.448 ns) + CELL(0.589 ns) = 1.037 ns; Loc. = LCCOMB_X26_Y12_N4; Fanout = 6; COMB Node = 'JISHU:u1\|74160:inst3\|45~14'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.037 ns" { JISHU:u1|74160:inst9|9 JISHU:u1|74160:inst3|45~14 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.370 ns) 1.805 ns JISHU:u1\|74160:inst4\|45~14 3 COMB LCCOMB_X26_Y12_N26 4 " "Info: 3: + IC(0.398 ns) + CELL(0.370 ns) = 1.805 ns; Loc. = LCCOMB_X26_Y12_N26; Fanout = 4; COMB Node = 'JISHU:u1\|74160:inst4\|45~14'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.768 ns" { JISHU:u1|74160:inst3|45~14 JISHU:u1|74160:inst4|45~14 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 976 1112 1176 1016 "45" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.206 ns) 2.716 ns JISHU:u1\|74160:inst4\|8~29 4 COMB LCCOMB_X27_Y12_N0 1 " "Info: 4: + IC(0.705 ns) + CELL(0.206 ns) = 2.716 ns; Loc. = LCCOMB_X27_Y12_N0; Fanout = 1; COMB Node = 'JISHU:u1\|74160:inst4\|8~29'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { JISHU:u1|74160:inst4|45~14 JISHU:u1|74160:inst4|8~29 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.824 ns JISHU:u1\|74160:inst4\|8 5 REG LCFF_X27_Y12_N1 3 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.824 ns; Loc. = LCFF_X27_Y12_N1; Fanout = 3; REG Node = 'JISHU:u1\|74160:inst4\|8'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { JISHU:u1|74160:inst4|8~29 JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.273 ns ( 45.08 % ) " "Info: Total cell delay = 1.273 ns ( 45.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.551 ns ( 54.92 % ) " "Info: Total interconnect delay = 1.551 ns ( 54.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { JISHU:u1|74160:inst9|9 JISHU:u1|74160:inst3|45~14 JISHU:u1|74160:inst4|45~14 JISHU:u1|74160:inst4|8~29 JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { JISHU:u1|74160:inst9|9 {} JISHU:u1|74160:inst3|45~14 {} JISHU:u1|74160:inst4|45~14 {} JISHU:u1|74160:inst4|8~29 {} JISHU:u1|74160:inst4|8 {} } { 0.000ns 0.448ns 0.398ns 0.705ns 0.000ns } { 0.000ns 0.589ns 0.370ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.769 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk1 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk1'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk1~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk1~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.769 ns JISHU:u1\|74160:inst4\|8 3 REG LCFF_X27_Y12_N1 3 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.769 ns; Loc. = LCFF_X27_Y12_N1; Fanout = 3; REG Node = 'JISHU:u1\|74160:inst4\|8'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk1~clkctrl JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.78 % ) " "Info: Total cell delay = 1.766 ns ( 63.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 36.22 % ) " "Info: Total interconnect delay = 1.003 ns ( 36.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.769 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.769 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst4|8 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.768 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk1 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk1'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk1~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk1~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.859 ns) + CELL(0.666 ns) 2.768 ns JISHU:u1\|74160:inst9\|9 3 REG LCFF_X26_Y12_N9 5 " "Info: 3: + IC(0.859 ns) + CELL(0.666 ns) = 2.768 ns; Loc. = LCFF_X26_Y12_N9; Fanout = 5; REG Node = 'JISHU:u1\|74160:inst9\|9'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.525 ns" { clk1~clkctrl JISHU:u1|74160:inst9|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.80 % ) " "Info: Total cell delay = 1.766 ns ( 63.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 36.20 % ) " "Info: Total interconnect delay = 1.002 ns ( 36.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst9|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst9|9 {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.769 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.769 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst4|8 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst9|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst9|9 {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "74160.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { JISHU:u1|74160:inst9|9 JISHU:u1|74160:inst3|45~14 JISHU:u1|74160:inst4|45~14 JISHU:u1|74160:inst4|8~29 JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { JISHU:u1|74160:inst9|9 {} JISHU:u1|74160:inst3|45~14 {} JISHU:u1|74160:inst4|45~14 {} JISHU:u1|74160:inst4|8~29 {} JISHU:u1|74160:inst4|8 {} } { 0.000ns 0.448ns 0.398ns 0.705ns 0.000ns } { 0.000ns 0.589ns 0.370ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.769 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst4|8 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.769 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst4|8 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk1 clk1~clkctrl JISHU:u1|74160:inst9|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} JISHU:u1|74160:inst9|9 {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK0 register register CNT4\[0\] CNT4\[1\] 340.02 MHz Internal " "Info: Clock \"CLK0\" Internal fmax is restricted to 340.02 MHz between source register \"CNT4\[0\]\" and destination register \"CNT4\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.789 ns + Longest register register " "Info: + Longest register to register delay is 0.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4\[0\] 1 REG LCFF_X26_Y12_N3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y12_N3; Fanout = 12; REG Node = 'CNT4\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.206 ns) 0.681 ns CNT4\[1\]~20 2 COMB LCCOMB_X26_Y12_N18 1 " "Info: 2: + IC(0.475 ns) + CELL(0.206 ns) = 0.681 ns; Loc. = LCCOMB_X26_Y12_N18; Fanout = 1; COMB Node = 'CNT4\[1\]~20'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.681 ns" { CNT4[0] CNT4[1]~20 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.789 ns CNT4\[1\] 3 REG LCFF_X26_Y12_N19 11 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.789 ns; Loc. = LCFF_X26_Y12_N19; Fanout = 11; REG Node = 'CNT4\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 39.80 % ) " "Info: Total cell delay = 0.314 ns ( 39.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.475 ns ( 60.20 % ) " "Info: Total interconnect delay = 0.475 ns ( 60.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { CNT4[0] CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.789 ns" { CNT4[0] {} CNT4[1]~20 {} CNT4[1] {} } { 0.000ns 0.475ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 destination 2.758 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK0\" to destination register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK0 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'CLK0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns CLK0~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'CLK0~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.859 ns) + CELL(0.666 ns) 2.758 ns CNT4\[1\] 3 REG LCFF_X26_Y12_N19 11 " "Info: 3: + IC(0.859 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X26_Y12_N19; Fanout = 11; REG Node = 'CNT4\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.525 ns" { CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.67 % ) " "Info: Total cell delay = 1.756 ns ( 63.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 36.33 % ) " "Info: Total interconnect delay = 1.002 ns ( 36.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK0 source 2.758 ns - Longest register " "Info: - Longest clock path from clock \"CLK0\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK0 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'CLK0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK0 } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns CLK0~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'CLK0~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK0 CLK0~clkctrl } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.859 ns) + CELL(0.666 ns) 2.758 ns CNT4\[0\] 3 REG LCFF_X26_Y12_N3 12 " "Info: 3: + IC(0.859 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X26_Y12_N3; Fanout = 12; REG Node = 'CNT4\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.525 ns" { CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.67 % ) " "Info: Total cell delay = 1.756 ns ( 63.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 36.33 % ) " "Info: Total interconnect delay = 1.002 ns ( 36.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { CNT4[0] CNT4[1]~20 CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.789 ns" { CNT4[0] {} CNT4[1]~20 {} CNT4[1] {} } { 0.000ns 0.475ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[1] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.758 ns" { CLK0 CLK0~clkctrl CNT4[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.758 ns" { CLK0 {} CLK0~combout {} CLK0~clkctrl {} CNT4[0] {} } { 0.000ns 0.000ns 0.143ns 0.859ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { CNT4[1] {} } { } { } "" } } { "JISHIXIANSHI.vhd" "" { Text "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vhd" 77 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
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