📄 ata2.h
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#ifndef CARD_IS_MMC
#define CPRM
#endif
//#define SECURE_VENDOR
//#define SECURE_PREFORMAT
/*--------------------------------------------------------------------------*/
/* General definitions */
/*--------------------------------------------------------------------------*/
#define DEBUG_DATA 0
#define SECTOR_SIZE 512
#define FALSE 0
#define TRUE 1
#define INDEFINITE 0xffffffffL
#define SECTOR_BUFFER (unsigned char *) 0xC8000000
/*--------------------------------------------------------------------------*/
/* CSD */
/*--------------------------------------------------------------------------*/
#ifdef CARD_IS_MMC
#define CSD_STRUCTURE 2 // Version 3.1-3.2
#define SPEC_VERS 3 // Version 3.1-3.2
#define TAAC 0x46 // 2.5 ms
#define NSAC 0x00
#define TRAN_SPEED 0x2A
#define CCC (0x035 | (1<<6) | (1<<8))
#define READ_BL_LEN 9
#define READ_BL_PARTIAL 1
#define WRITE_BLK_MISALIGN 0
#define READ_BLK_MISALIGN 0
#define DSR_IMP 0
#define C_SIZE 3983
// #define C_SIZE 1959
#define VDD_R_CURR_MIN 6
#define VDD_R_CURR_MAX 6
#define VDD_W_CURR_MIN 6
#define VDD_W_CURR_MAX 6
#define C_SIZE_MULT 2
//#define C_SIZE_MULT 1
#define ERASE_GRP_SIZE 0x00
#define ERASE_GRP_MULT 0x0f
#define WP_GRP_SIZE 0x00
#define WP_GRP_ENABLE 1
#define DEFAULT_ECC 0
#define R2W_FACTOR 5
#define WRITE_BL_LEN 0x9
#define WRITE_BL_PARTIAL 0
#define CONTENT_PROT_APP 0
#define FILE_FORMAT_GRP 0
#define COPY 0
#define PERM_WRITE_PROTECT 0
#define TMP_WRITE_PROTECT 0
#define FILE_FORMAT 0
#define ECC 0
#else
#define CSD_STRUCTURE 0 // Version 1.0
#define TAAC 0x36 // 2.5 ms
#define NSAC 0x00
#define TRAN_SPEED 0x32 // 25 Mbits/s
#define CCC ((1<<0)|(1<<2)|(1<<4)|(1<<5)|(1<<8)| (1<<6))
#define READ_BL_LEN 9
#define READ_BL_PARTIAL 1
#define WRITE_BLK_MISALIGN 0
#define READ_BLK_MISALIGN 0
#define DSR_IMP 0
#define C_SIZE 1889
#define VDD_R_CURR_MIN 4
#define VDD_R_CURR_MAX 4
#define VDD_W_CURR_MIN 4
#define VDD_W_CURR_MAX 4
#define C_SIZE_MULT 3
#define ERASE_BLK_ENABLE 1
#define SECTOR_SIZE_II 0x0f
#define WP_GRP_SIZE 0x00
#define WP_GRP_ENABLE 1
#define R2W_FACTOR 5
#define WRITE_BL_LEN 0x9
#define WRITE_BL_PARTIAL 0
#define FILE_FORMAT_GRP 0
#define COPY 0
#define PERM_WRITE_PROTECT 0
#define TMP_WRITE_PROTECT 0
#define FILE_FORMAT 0
#endif
/*--------------------------------------------------------------------------*/
/* Global Registers and variables */
/*--------------------------------------------------------------------------*/
register unsigned int EventFlags asm("G6"); /* for rtk and nortk */
register unsigned int BCRShadow asm("G10");
register unsigned int FCRShadow asm("G11");
register unsigned int MCRShadow asm("G12");
#define CvtByteOrder32(Value) Value
#define CvtByteOrder16(Value) Value
extern unsigned int SkipErase;
/*--------------------------------------------------------------------------*/
/* Types */
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* Error Codes */
/*--------------------------------------------------------------------------*/
#define NO_ERROR 0 // ErrorCodes
#define ERROR 1
#define NOT_FOUND_ERROR 1
#define ERASE_ERROR 2
#define WRITE_ERROR 3
#define READ_ERROR 4
#define MISALIGNED_ERROR 5
#define WRITEPROTECT_ERROR 6
#define ERASE_SKIP_ERROR 7
#define CID_CSD_OVERWRITE (1<<1)
/*--------------------------------------------------------------------------*/
/* Define Addresses of Registers in SD interface */
/*--------------------------------------------------------------------------*/
#define SETUP0 (0<<8)
#define SETUP2 (1<<8)
#define SETUP6 (3<<8)
#ifndef ACCESS2
#define ACCESS2 (0<<5)
#define ACCESS4 (1<<5)
#define ACCESS6 (2<<5)
#define ACCESS16 (7<<5)
#endif
#define HOLD2 (1<<3)
#define HOLD4 (2<<3)
#define HOLD6 (3<<3)
#define IO_TIMING (SETUP0+ACCESS2+HOLD2)
//#define IO_TIMING ((15<<4)+HOLD2)
#define FPGA_ADDR ((1<<25)|(1<<27)|IO_TIMING)
#define FPGA_BUFFER (FPGA_ADDR|(0<<22))
#define FPGA_INTREG (FPGA_ADDR|(1<<22))
#define FPGA_BITSET (FPGA_ADDR|(2<<22))
#define FPGA_ADDREG (FPGA_ADDR|(2<<22))
#define FPGA_ERASEREG (FPGA_ADDR|(3<<22))
#define FPGA_BITCLR (FPGA_ADDR|(3<<22))
#define FPGA_DEBUGADDR (FPGA_ADDR|(4<<22))
#define FPGA_REGADDR (FPGA_ADDR|(5<<22))
#define FPGA_CMD_MSB (FPGA_ADDR|(4<<22))
#define FPGA_CMD_LSB (FPGA_ADDR|(5<<22))
#define FPGA_RES_MSB (FPGA_ADDR|(6<<22))
#define FPGA_RES_LSB (FPGA_ADDR|(7<<22))
#define EXCHANGE_BUFFER_ADDR (FPGA_REGADDR | (11<<13))
#define STATUS_ADDR (FPGA_REGADDR | (9<<13))
#define MMCREG_ADDR (FPGA_REGADDR | (10<<13))
#define ENABLE_ADDR (FPGA_REGADDR | (12<<13))
#define LAST_SECTOR_ADDR (FPGA_REGADDR | (13<<13))
#define OCR_ADDR (FPGA_REGADDR)
#define OCR_COMPARE_ADDR (FPGA_REGADDR | (14<<13))
/*--------------------------------------------------------------------------*/
/* Bit definitions and macros for the SD interrupt register */
/*--------------------------------------------------------------------------*/
#define HY_READ (1<<0)
#define HY_WRITE (1<<1)
#define HY_CLEAR (1<<2)
#define HY_STOP (1<<3)
#define HY_AGAIN (1<<4)
#define HY_READY (1<<5)
#define HY_NON_STOP (1<<6)
#define HY_RESET (1<<7)
#define HY_PRG_READY (1<<8)
#define HY_DEBUG_CMD (1<<9)
#define HY_DEBUG_RES (1<<10)
#define HY_CNT_READY (1<<11)
#define HY_AUTH (1<<12)
#define HY_CMD (1<<13)
#define FPGA_RESET (1<<14)
#define BUS_WIDTH (1<<16)
#define READ_INTREG() inp8(FPGA_INTREG)
#define READ_INTREG_SLOW() inp8(FPGA_INTREG|(15<<4))
#define READ_FLREG() inp8(FPGA_FLREG)
#define CLEAR_DUMMY() outpw0(FPGA_INTREG); outpw0(FPGA_INTREG)
#define CLEAR_HY_READ() outpw0(FPGA_INTREG|(HY_READ<<13))
#define CLEAR_HY_WRITE() outpw0(FPGA_INTREG+(HY_WRITE<<13))
#define CLEAR_HY_CLEAR() outpw0(FPGA_INTREG+(HY_CLEAR<<13))
#define CLEAR_HY_STOP() outpw0(FPGA_INTREG+(HY_STOP<<13))
#define CLEAR_HY_AGAIN() outpw0(FPGA_INTREG+(HY_AGAIN<<13))
#define SET_HY_READY() outpw0(FPGA_INTREG+(HY_READY<<13))
#define SET_HY_PRG_READY() outpw0(FPGA_INTREG+(HY_PRG_READY<<13))
#define CLEAR_HY_RESET() outpw0(FPGA_INTREG+(HY_RESET<<13))
#define CLEAR_INT_LOW() outpw0(FPGA_INTREG+(31<<13))
#define CLEAR_INT_HIGH() outpw0(FPGA_DEBUGADDR+(35<<13))
#define CLEAR_HY_DEBUG_CMD() outpw0(FPGA_DEBUGADDR+(1<<13))
#define CLEAR_HY_DEBUG_RES() outpw0(FPGA_DEBUGADDR+(1<<14))
#define CLEAR_HY_DEBUG_INT() outpw0(FPGA_DEBUGADDR+(1<<13)+(1<<14))
//#define SET_HY_OOR() outpw0(FPGA_DEBUGADDR+(1<<15))
#define SET_HY_CNT_READY() outpw0(FPGA_DEBUGADDR+(1<<16))
#define SET_HY_AUTH() outpw0(FPGA_DEBUGADDR+(1<<17))
#define CLEAR_HY_CMD() outpw0(FPGA_DEBUGADDR+(1<<18))
#define EXCHANGE_BUFFERS() outpw0(EXCHANGE_BUFFER_ADDR)
/*--------------------------------------------------------------------------*/
/* Macros for others SD registers */
/*--------------------------------------------------------------------------*/
#define EXCHANGE_BUFFERS() outpw0(EXCHANGE_BUFFER_ADDR)
#define READ_ADDRESS() inp8(FPGA_ADDREG)
#define READ_ERASE_END() inp8(FPGA_ERASEREG)
#define READ_SECOND_ARGUMENT() inp8(FPGA_ERASEREG)
#define READ_CMD_MSB() inp8(FPGA_CMD_MSB)
#define READ_CMD_LSB() inp8(FPGA_CMD_LSB)
#define READ_RES_MSB() inp8(FPGA_RES_MSB)
#define READ_RES_LSB() inp8(FPGA_RES_LSB)
#define ENABLE_RSFSM() outpw2r(ENABLE_ADDR, 1)
#define ENABLE_SSFSM() outpw2r(ENABLE_ADDR, 2)
#define DISABLE_FSMS() outpw2r(ENABLE_ADDR, 0)
#define WRITE_OCR_COMPARE(a) outpw2r(OCR_COMPARE_ADDR, a)
#define RSFSM_STATE() ((READ_CMD_LSB() >>11) & 0x1f)
#define SSFSM_STATE() ((READ_CMD_LSB() >>7) & 0xf)
#define FSM_STATE() ((READ_CMD_LSB() >>16 ) & 0xff)
#define LAST_COMMAND() ((READ_CMD_MSB() >>24 ) & 0x3f)
/*--------------------------------------------------------------------------*/
/* Event definitions and Macros */
/*--------------------------------------------------------------------------*/
#define EVENT(x) (EventFlags & (x))
#define SET_EVENT(x) EventFlags |= (x)
#define RESET_EVENT(x) EventFlags &= ~(x)
#define TIMER_EVENT (1<<0) // EventFlags
#define CLEARGUARD_EVENT (1<<1)
#define COMMAND_EVENT (1<<2)
#define DRQ_EVENT (1<<3)
#define AGAIN_EVENT (1<<3)
#define SOFTRESET_EVENT (1<<4)
#define STOP_EVENT (1<<4)
#define PCMCIARESET_EVENT (1<<5)
#define SOFTRESETOFF_EVENT (1<<6)
#define STARTUP_ACTIVE_EVENT (1<<7)
#define FLASH_EVENT (1<<8) // Bits 8..12 for 5 InterruptSources
#define REPEAT_BIT (1<<29)
#define READ_BIT (1<<30)
#define DEBUG_EVENT (1<<31)
#define PC_EVENT (COMMAND_EVENT|STOP_EVENT|AGAIN_EVENT)
/*--------------------------------------------------------------------------*/
/* OP. Codes */
/*--------------------------------------------------------------------------*/
#define READ_OPC 0 // device independent opcodes
#define WRITE_OPC 1
#define ERASE_OPC 2
#define READ_STATUS_OPC 3
#define SPECIALWRITE_OPC 4
#define VENDOR_OPC 5
// OPC for LogToPhys1
#define INTERNAL_READ_OPC 5
#define USER_AREA_READ 0
#define USER_AREA_WRITE 0
#define MID_READ 1
#define MKB_READ 2
#define WRITE_CSD 1
#define GET_CER_RESPONSE_1 3
#define SET_CER_RANDOM_1 3
#define GET_CER_RANDOM_2 4
#define SET_CER_RESPONSE_2 4
#define SECURE_READ 5
#define SECURE_WRITE 5
#define COMMAND_56_WRITE 6
#define NUMBER_WRITTEN_SECTORS 7
#define SET_PRE_ERASE 7
#define SDSTATUS 8
#define CHANGE_SECURE_AREA 8
#define SD_CONF_REGISTER 9
#define WRITE_MKB 9
#define COUNT_READ 10
#define COUNT_WRITE 10
#define READ_WRITE_PROTECT 11
#define SET_WRITE_PROTECT 11
#define CLEAR_WRITE_PROTECT 12
#define PHYS_READ 0
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