📄 samsung_old.asm
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BE ExitWaitForReady ; Yes: --> branch
MOVI L4, FlashReadyEvent ;
WaitGuard ; Wait until EraseDone
ANDNI EventFlags, FlashReadyEvent ;
ExitWaitForReady:
RET PC, L1 ;
;============================================================================;
; Function : _SetOverlappedTrapEntry (TRAP 30) ;
; ;
; Registers : L0 : Sector# ;
; L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
;============================================================================;
_SetOverlappedTrapEntry: ;
FRAME L4, L1 ;
LDHU.D PC, L0, #_ActChipNumber2-PC ; Chip# * 2
SHRI L0, 1 ; Chip#
MOVI L3, OverlappedEvent ;
SHL L3, L0 ; OverlappedEvent for Chip
OR OverlappedFlags, L3 ; overlapped Operation for
ADDI OverlappedFlags, 1 ; ActiveFlashChips++
RET PC, L1 ; this Chip
;============================================================================;
; Function : _WriteChunkTrapEntry (TRAP 29) ;
; ;
; Registers : L0 : BufferAddress ;
; L1 : Length of Chunk ;
; L2 : Flags ;
; L3 : ChipSelect ;
; L4 : Return-PC ;
; L5 : Return-SR ;
; L6 : Temp ;
; L7 : Temp ;
;============================================================================;
_WriteChunkTrapEntry:
; FRAME L8, L4
FRAME L10, L4
ORI L3, FLASH_ECC_ENABLE ; Enable Syndrome Unit
STW.IOA 0, 0, RESET_PARITY ; Clear Paritybytes b3..b0
STW.IOA 0, 0, SM_RESET_PARITY ; Clear SM Paritybytes
LDW.P L0, L6 ; first read
LDW.P L0, L7 ; first read
ADDI L1, -8 ; decrement counter
BE WriteLastBytes ;
WriteLoop: STW.R L3, L6 ;
LDW.P L0, L6 ;
ADDI L1, -8 ; decrement counter
STW.R L3, L7 ;
DBNE WriteLoop ; ready?
LDW.P L0, L7 ;
WriteLastBytes: ;
STW.R L3, L6 ; store last bytes
STW.R L3, L7 ; store last bytes
LDW.IOA 0, L6, READ_B3_B2 ; Read Paritybytes b3, b2
LDW.IOA 0, L7, READ_B1_B0 ; Read Paritybytes b0, b1
CMPBI L2, WITH_ECC ; With ECC->516-Byte-Buffer?
BNE WriteECC ; Yes: -> branch
CMPBI L2, READ_WRITE_LONG ; With 528-Byte-Buffer?
BE WriteECC ; No: -> branch
LDHU.N L0, L6, 2 ; Load Paritybytes from Buffer
LDHU.N L0, L7, 2 ;
WriteECC:
STHU.D L3, L6, 0 ; Store Paritybytes b3, b2
STHU.D L3, L7, 0 ; Store Paritybytes b1, b0
CMPBI L2, WITH_CRC ; With CRC?
BE WriteNoCRC ; No: --> branch
LDW.IOA 0, L6, SM_PARITY_EVEN ; Read Paritybytes Even
LDW.IOA 0, L7, SM_PARITY_ODD ; Read Paritybytes Odd
STHU.D L3, L6, 0 ; Store Parity Even
STHU.D L3, L7, 0 ; Store Parity Odd
WriteNoCRC: ANDNI L3, FLASH_ECC_ENABLE ; Disable Parity Unit
RET PC, L4 ;
;============================================================================;
; Function : _ReadChunkTrapEntry (TRAP 28) ;
; ;
; Registers : L0 : BufferAddress ;
; L1 : Length of Chunk ;
; L2 : Flags ;
; L3 : ChipSelect ;
; L4 : Return-PC ;
; L5 : Return-SR ;
; L6 : Temp ;
; L7 : Temp ;
;============================================================================;
_ReadChunkTrapEntry:
FRAME L13, L4
ORI L3, FLASH_ECC_ENABLE ; Enable Syndrome Unit
STW.IOA 0, 0, WRITE_S1_S0 ; Clear Syndromebytes s1, s0
STW.IOA 0, 0, WRITE_S3_S2 ; Clear Syndromebytes s3, s2
STW.IOA 0, 0, SM_RESET_PARITY ; Clear SM Paritybytes
MOVD L11, L0 ; Save BufferAddr/ChunkLength
SUM L6, L1, 4 ; ChunkLength+4 (Paritybytes)
STW.IOA 0, L6, WRITE_FF_COUNTER ; Init FF_Counter
LDW.R L3, L6 ; first read
LDW.R L3, L7 ; first read
ADDI L1, -8 ; decrement counter
BE ReadLastBytes ;
ReadLoop: STW.P L0, L6 ;
LDW.R L3, L6 ;
ADDI L1, -8 ; decrement counter
STW.P L0, L7 ;
DBNE ReadLoop ; ready?
LDW.R L3, L7 ;
ReadLastBytes: ;
STD.P L0, L6 ; store last bytes
;
LDHU.D L3, L7, 0 ; read ParityBytes
LDHU.D L3, L8, 0 ; read ParityBytes
CMPBI L2, READ_WRITE_LONG|WITH_CRC; Store ParityBytes in Buffer?
BE ReadFFCounter ; No: -> branch
SHLI L7, 16
ADD L7, L8
STW.R L0, L7 ; Store ParityBytes
CMPBI L2, READ_WRITE_LONG ; BufferAddress+=4?
BE ReadFFCounter ; No: -> branch
ADDI L0, 4 ;
ReadFFCounter:
LDW.IOA 0, L6, READ_FF_COUNTER ;
MASK L9, L2, WITH_ECC ; 0/2
CMP L6, L9 ; FF_Counter <= 0/2?
SETLE L6 ; Yes:->EraseBit this Chunk=1
LDBU.D PC, L9, #_ChunkErased-PC ;
SHLI L9, 1 ;
OR L9, L6 ; ChunkErased |=
; (ErasedBit this Chunk)
STBU.D PC, L9, #_ChunkErased-PC ;
;
MOV L1, L12 ; Restore ChunkLength
MOVI L10, 0 ; ECC_Flag = FALSE
CMPI L6, 1 ; ChunkErased?
BE ExitReadChunk ; Yes: --> branch, no ECC Calc.
STBU.D PC, 0, #_SectorErased-PC ; SectorErased = FALSE
CMPBI L2, WITH_ECC ; With ECC?
BE ExitReadChunk ; No: -> branch
LDW.IOA 0, L6, READ_S1_S0 ; Read SyndromeBytes s0, s1
LDW.IOA 0, L7, READ_S3_S2 ; Read SyndromeBytes s3, s2
MOVD L9, L6 ; All SyndromeBytes == 0?
BE ExitReadChunk ; Yes: --> branch
; Par1: s0,s1
; Par2: s2,s3
; Par3: Begin of this Chunk
; Par4: ChunkSize
if NORTK==0
CALL L13, 0, _correct ; ErrorCorrection
else
CALL L13, 0, #_correct ; ErrorCorrection
endif
CMPBI L2, ERROR_IF_ECC_NEEDED ;
DBNE ExitReadChunk ;
MOVI L10, 1 ; Error, if ErrorCorrection
; needed
CMPI L9, 3 ; uncorrectable Error?
SETE L10 ; ECC_Flag for this Chunk
ExitReadChunk: ;
CMPBI L2, WITH_CRC ; With CRC?
BE ExitReadChunk1 ; No: --> branch
ANDNI L3, FLASH_SM_ENABLE ; Disable SmartMedia Unit
LDHU.D L3, L8, 0 ; Load Parity Even
LDHU.D L3, L9, 0 ; Load Parity Odd
CMPI L10, 0 ; uncorrectable error?
BNE ExitReadChunk1 ; Yes: --> branch
LDBU.D PC, L12, #_ChunkErased-PC ;
CMPBI L12, 1 ; Actual Chunk Erased?
BNE ExitReadChunk1 ; Yes: --> branch
MOVD L6, L6 ; SyndromeBytes == 0?
BE SkipRecalculateCRC ; Yes: --> branch
MOVD L10, L0 ; Par1: L10=BufferAddress
SUB L10, L1 ;
; Par2: L11=ChunkLength
MOV L12, L3 ; Par3: L12=ChipSelect
if NORTK==0
CALL L13, 0, _RecalculateCRC ;
else
CALL L13, 0, #_RecalculateCRC ;
endif
SkipRecalculateCRC:
LDW.IOA 0, L10, SM_PARITY_EVEN ; Read Paritybytes Even
LDW.IOA 0, L11, SM_PARITY_ODD ; Read Paritybytes Odd
SUB L8, L10 ; Compare Even Parity
SUBC L9, L11 ; Compare Odd Parity
SETNE L10 ; L10 = 1(error), if not equal
ExitReadChunk1:
LDBU.D PC, L7, #_ChunkECC-PC ;
SHLI L7, 1 ;
OR L7, L10 ; ECC_Flag for this Chunk
STBU.D PC, L7, #_ChunkECC-PC ;
ANDNI L3, FLASH_ECC_ENABLE ; Disable Parity Unit
RET PC, L4 ;
;============================================================================;
; Function : _ReadDeviceIdTrapEntry (TRAP 26) ;
; ;
; Registers : L0 : ChipSelect ;
; : L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
; L4 : Temp ;
;============================================================================;
_ReadDeviceIdTrapEntry:
FRAME L5, L1
LDBU.A 0, L3, _DeviceIdAddress
STBU.D L0, L3, SAM_ALE_BIT|B16 ; Write ColumnAddress = 0
STBU.D L0, 0, FLASH_INHIBIT|B16 ; Delay ALE to RE
LDBU.D L0, L3, B16 ; Read Maker Code ($EC)
LDBU.D L0, L4, B16 ; Read Device Code
SHLI L3, 8 ;
OR L3, L4 ; Merge both codes
LDBU.D L0, L4, B16 ; Read Device Code
STBU.D PC, L4, #_DeviceId1-PC ;
LDBU.D L0, L4, B16 ; Read Device Code
STBU.D PC, L4, #_DeviceId2-PC ;
LDBU.D L0, L4, B16 ; Read Device Code
STBU.D PC, L4, #_DeviceId3-PC ;
MOV L0, L3 ; return DeviceID
RET PC, L1 ;
;============================================================================;
; Function : _SectorToPageTrapEntry (TRAP 25) ;
; ;
; Registers : L0 : Sector# --> Page# ;
; L1 : ChipSelect ;
; L2 : Return-PC ;
; L3 : Return-SR ;
;============================================================================;
_SectorToPageTrapEntry:
FRAME L4, L2
RET PC, L2 ;
;============================================================================;
; Function : _NextSectorTrapEntry (TRAP 24) ;
; ;
; Registers : L0 : NextSector# for ReadAhead ;
; L1 : ChipSelect ;
; L2 : Return-PC ;
; L3 : Return-SR ;
; L3 : Return-SR ;
;============================================================================;
_NextSectorTrapEntry:
FRAME L5, L2
LDHU.D PC, L4, #_ActChipNumber2-PC ; Chip# * 2
ADDI L4, _ColAddr ;
STHU.D L4, 0, 0 ; ColAddr[ActChip#] = 0
if NORTK==1
LDW.A 0, L0, #_NextSectorNumber ; NextSector# for ReadAhead
else
LDW.A 0, L0, _NextSectorNumber ; NextSector# for ReadAhead
endif
RET PC, L2 ;
;============================================================================;
; Function : _SetColumnTrapEntry (TRAP 23) ;
; ;
; Registers : L0 : PageBitMask ;
; L2 : Opc ;
; L3 : Sector# ;
; L4 : ChipSelect ;
; L5 : Return-PC ;
; L6 : Return-SR ;
; L7 : BitMask ;
; L8 : Col ;
;============================================================================;
_SetColumnTrapEntry:
FRAME L9, L4
MOVI L8, 0 ; Col = 0
MOVI L7, 1 ; BitMask = 1
SetColLoop: CMPB L0, L7 ; PageBitMask & BitMask?
BNE StoreCol ; Yes:--> branch
SHLI L7, 1 ; Bitmask<<1
DBR SetColLoop ; Loop
ADDI L8, PHYS_SECTOR_SIZE ; Col += SectorSize
StoreCol: ANDN L0, L7 ; delete lowest 1 in PageBitMask
LDHU.D PC, L7, #_ActChipNumber2-PC ; Chip# * 2
ADDI L7, _ColAddr ;
STHU.D L7, L8, 0 ; ColAddr[ActChip#] = Col
RET PC, L4 ;
;============================================================================;
; Function : _ClearSectorTrapEntry (TRAP 22) ;
; ;
; Registers : L0 : ChipSelect ;
; L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : LoopCount ;
; L4 : WriteValue ;
;============================================================================;
_ClearSectorTrapEntry:
FRAME L9, L1
MOVI L3, PHYS_SECTOR_BYTES ; LoopCount
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