📄 samsung_old.asm
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; L1 : alternate ReturnAddress (in), PageNumber (out) ;
; L2 : SectorNumber (in), ChipSelect (out) ;
; L3 : Return-PC ;
; L4 : Return-SR ;
; L5 : ChipNumber ;
; L6 : Temp ;
; L7 : Temp ;
; L8 : Temp ;
;============================================================================;
_ChipSelectTrapEntry:
FRAME L9, L3
MOVI L8, 0 ; Default Col
XX2 L5, L0, 0 ;
ADDI L5, _ColTab ;
LDHU.D L5, L5, 0 ;
MOV L7, L0 ;
ADDI L7, _OpcTab ;
LDBU.D L7, L0, 0 ; Opc = OpcodeTab[Opc]
ADD L8, L5 ; Col += ColTab[Opc]
MASK L5, L2, CHIPNO ; Extract Chip No
SHRI L5, CHIPNO_SHIFT ; Shift ChipNo right
XX2 L7, L5, 0 ; Chip# * 2
STHU.D PC, L7, #_ActChipNumber2-PC ; Chip# * 2
MOVI L6, SAM_SELECT_CHIP0 ; Chip Select bit for Chip 0
SHL L6, L5 ; shift Chip Select
XORI L6, SAM_BASE_ADDR ; and add address bits
STW.D PC, L6, #_ActChipSelect-PC ;
ADDI L7, _ColAddr ;
STHU.D L7, L8, 0 ; ColAddr[ActChip#] = Col
MASK L6, OverlappedFlags, OverlappedEvent-1
CMPI L6, MAX_ACTIVE_CHIPS ; too much chips are busy?
BLT ChipSelectTestBusy ; No: --> branch
MOVI L8, FlashReadyEvent ;
ANDN EventFlags, L8 ; if OverlappedFlags is
; already deleted, FlashReadyEvent may still be pending
WaitGuard ; until Busy Chips < 4
ChipSelectTestBusy:
MOVI L6, OverlappedEvent ;
SHL L6, L5 ; OverlappedEvent[ChipNumber]
CMPB OverlappedFlags, L6 ; This Chip is idle?
BE SkipWaitGuard ; Yes:--> branch
MOVI L8, FlashReadyEvent ;
ANDN EventFlags, L8 ; if OverlappedFlags is
; already deleted, FlashReadyEvent may still be pending
WaitGuard ; Wait until Erase/ProgramDone
if ASSERT
ORI SR, HFLAG ;
MOV L6, ISR ; Read Input-Status-Register
CMPBI L6, IO1Level ; READY = High ?
trape 60 ; No: --> error
endif
SkipWaitGuard: ;
ANDNI EventFlags, FlashReadyEvent ; if OverlappedFlags is
; already deleted, FlashReadyEvent may still be pending
MOV L1, L2 ; return ActPage#
LDW.D PC, L2, #_ActChipSelect-PC ;
if NORTK==0
ORI L4, LFLAG ; LockFlag in Return-SR
endif
RET PC, L3 ;
;============================================================================;
; Function : _FlashIdleTrapEntry (TRAP 38) ;
; ;
; Registers : L0 : Sector#/ChipNumber (in) ;
; L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
;============================================================================;
_FlashIdle1TrapEntry:
_FlashIdleTrapEntry:
FRAME L4, L1 ; Par = ChipNumber/Sector#
MOVI L3, FLASH_IDLE ;
STW.R L3, 0 ; ChipIdle
RET PC, L1 ;
;============================================================================;
; Function : _SetOpcTrapEntry (TRAP 37) ;
; ;
; Registers : L0 : Opc ;
; L1 : Sector# ;
; L2 : ChipSelect ;
; L3 : Return-PC ;
; L4 : Return-SR ;
; L5 : Temp ;
;============================================================================;
_SetOpcTrapEntry: ;
FRAME L8, L3 ;
if ASSERT
MASK L5, L0, $ff
CMPI L5, WRITE_SECTOR_OPC ;
BE EndAssert
CMPI L5, PROGRAM_SECTOR_OPC ;
BE EndAssert
CMPI L5, CACHE_PROGRAM_OPC ;
BE EndAssert
CMPI L5, RANDOM_DATA_INPUT_OPC ;
BE EndAssert
LDHU.D PC, L5, #_ActChipNumber2-PC
SHRI L5, 1
LDBU.D PC, L6, #_PendingWriteChipNumber-PC
CMP L5, L6
TRAPE 60
EndAssert:
endif
MASK L6, L0, ~DONT_SAVE_OPC ;
ADDI L6, _FlashOpc ;
LDBU.D L6, L6, 0 ; Hardware Command code
CMPI L6, SKIP ; omit this opcode?
BE SetOpcExit ; Yes: --> Branch
STBU.D L2, L6, SAM_CLE_BIT|B16 ; Write Command
LDBU.D L2, L6, FLASH_INHIBIT|B16 ; Set AddressBus
MOV L6, L6 ;
SetOpc1: CMPBI L0, DONT_SAVE_OPC ; Save Opc in FlashState?
DBNE SetOpcExit ; No: --> Branch
ANDNI L0, DONT_SAVE_OPC ; Clear DontsaveOpc-Bit
LDHU.D PC, L5, #_ActChipNumber2-PC ; Chip# * 2
SHRI L5, 1 ; Chip#
ADDI L5, _FlashState ;
STBU.D L5, L0, 0 ; FlashState[Chip#] = Opc
SetOpcExit: ANDNI L0, DONT_SAVE_OPC ; Clear DontSaveOpc-Bit
RET PC, L3 ;
;============================================================================;
; Function : _SetAddrTrapEntry (TRAP 36) ;
; ;
; Registers : L0 : Opc ;
; L1 : Sector# ;
; L2 : ChipSelect ;
; L3 : Return-PC ;
; L4 : Return-SR ;
; L5 : Temp ;
; L6 : Temp ;
;============================================================================;
_SetAddrTrapEntry: ;
FRAME L7, L3 ;
ANDNI L1, CHIPNO ; Delete Chip No
SUM L5, L0, _NumberOfColBytes ;
LDBU.D L5, L5, 0 ; Bytes for ColumnAddress
CMPI L5, 0 ; No ColumnAddress?
BE SetAddr1 ; Yes: --> branch
LDHU.D PC, L6, #_ActChipNumber2-PC ; Chip# * 2
ADDI L6, _ColAddr ;
LDHU.D L6, L6, 0 ; Col = ColAddr[ActChip#]
ColLoop: STBU.D L2, L6, SAM_ALE_BIT|B16 ; Write ColumnAddress
ADDI L5, -1 ; Decrement ColAddressCounter
DBNE ColLoop ;
SHRI L6, 8 ; Next Byte of ColAddress
SetAddr1: SUM L5, L0, _NumberOfAddrBytes ;
LDBU.D L5, L5, 0 ; Bytes for RowAddress
CMPI L5, 0 ; No RowAddress?
BE SetAddr2 ; Yes: --> branch
RowLoop: STBU.D L2, L1, SAM_ALE_BIT|B16 ; Write RowAddress
ADDI L5, -1 ; Decrement RowAddressCounter
DBNE RowLoop ;
SHRI L1, 8 ; Next Byte of RowAddress
SetAddr2: LDBU.D L2, L5, FLASH_INHIBIT|B16 ; Set AddressBus
MOV L5, L5 ;
RET PC, L3 ;
;============================================================================;
; Function : _PollForReadyTrapEntry (TRAP 35) ;
; ;
; Registers : L0 : ChipSelect (Interrupt-Source) ;
; : L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
;============================================================================;
_PollForReadyTrapEntry: ;
FRAME L4, L1 ;
PollLoop: ORI SR, HFLAG ;
MOV L3, ISR ; Read Input-Status-Register
CMPBI L3, IO1Level ; READY = High ?
BZ PollLoop ; No: --> Loop again
RET PC, L1 ;
;============================================================================;
; Function : _ReadStatusTrapEntry (TRAP 34) ;
; ;
; Registers : L0 : ChipSelect/Status ;
; L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
;============================================================================;
_ReadStatusTrapEntry: ;
FRAME L4, L1 ;
MOVI L3, READ_STATUS ; Read-Status-Command
STBU.D L0, L3, SAM_CLE_BIT|B16 ; Write Command
;
LDBU.D L0, L0, B16 ; Read Status
ANDNI L0, $c0 ; clear ReadyBit,
; NotProtectedBit
RET PC, L1 ;
;============================================================================;
; Function : _ReadWordTrapEntry (TRAP 33) ;
; ;
; Registers : L0 : BufferAddress ;
; L1 : Flags ;
; L2 : ChipSelect/Word ;
; L3 : Return-PC ;
; L4 : Return-SR ;
;============================================================================;
_ReadWordTrapEntry: ;
FRAME L7, L3 ;
ORI L2, FLASH_ECC_ENABLE ; Enable Syndrome Unit
LDW.R L2, L2 ; Read Word from Flash
STW.D PC, L2, #_ERASE_COUNT - PC ; EraseCount
CMPBI L1, READ_WRITE_LONG ; Write Overhead to Buffer?
BE ReadWordExit ; No:--> branch
STW.P L0, L2 ;
ReadWordExit:
RET PC, L3 ;
;============================================================================;
; Function : _WriteWordTrapEntry (TRAP 32) ;
; ;
; Registers : L0 : Flags ;
; L1 : Word ;
; L2 : ChipSelect ;
; L3 : Return-PC ;
; L4 : Return-SR ;
; L5 : First ParityWord ;
; L6 : Second ParityWord ;
;============================================================================;
_WriteWordTrapEntry: ;
FRAME L8, L3 ;
CMPBI L0, SKIP_PROGRAM ; Write with programOp?
DBE WritePendingNumber ; No: --> branch
MOVI L5, NO_PENDING_WRITE ;
LDHU.D PC, L5, #_ActChipNumber2-PC ; Chip# * 2
SHRI L5, 1 ; Chip#
WritePendingNumber:
if ASSERT
LDBU.D PC, L6, #_PendingWriteChipNumber-PC
CMPI L6, NO_PENDING_WRITE
BE xxx
CMP L5, L6
TRAPNE 60
xxx:
endif
STBU.D PC, L5, #_PendingWriteChipNumber-PC
ORI L2, FLASH_ECC_ENABLE ; Enable Syndrome Unit
CMPBI L0, WRITE_WORD_ECC ; Overhead with ECC?
BNE WriteWord1 ; Yes:--> branch
STW.R L2, L1 ; Write Word to Flash
ANDNI L2, FLASH_ECC_ENABLE ; Disable Parity Unit
RET PC, L3 ;
WriteWord1:
STW.IOA 0, 0, RESET_PARITY ; Clear Paritybytes b3..b0
STW.IOA 0, 0, SM_RESET_PARITY ; Clear SM Paritybytes
STW.R L2, L1 ; Write Word to Flash
STW.R L2, L1 ; Write Word to Flash
; ReadOverheadECC uses ChunkSize=8
LDW.IOA 0, L5, READ_B3_B2 ; Read Paritybytes b3, b2
LDW.IOA 0, L6, READ_B1_B0 ; Read Paritybytes b0, b1
STHU.D L2, L5, 0 ; Store Paritybytes b3, b2
STHU.D L2, L6, 0 ; Store Paritybytes b1, b0
LDW.IOA 0, L5, SM_PARITY_EVEN ; Read Paritybytes Even
LDW.IOA 0, L6, SM_PARITY_ODD ; Read Paritybytes Odd
STHU.D L2, L5, 0 ; Store CRC-Parity Even
STHU.D L2, L6, 0 ; Store CRC-Parity Odd
if INV_BACKPTR_524
CMPBI L0, WRITE_OVERHEAD ; Overhead at EndOfSector?
BE WriteWord2 ; No:--> branch
LDW.A 0, L5, _NumberOfFFBytes ;
MOVI L6, -1 ; ErasedPattern
WriteWordLoop:
STW.R L2, L6 ; Write ErasedPattern to Flash
ADDI L5, -4 ; All FFBytes written?
BNE WriteWordLoop ; No:--> repeat
STW.R L2, L1 ; Write OverheadWord to Flash
WriteWord2:
endif
ANDNI L2, FLASH_ECC_ENABLE ; Disable Parity Unit
RET PC, L3 ;
;============================================================================;
; Function : _WaitForReadyTrapEntry (TRAP 31) ;
; ;
; Registers : L0 : Sector# (Interrupt-Source) ;
; : L1 : Return-PC ;
; L2 : Return-SR ;
; L3 : Temp ;
; L4 : Temp ;
;============================================================================;
_WaitForReadyTrapEntry: ;
FRAME L5, L1 ;
MOVI L3, 3 << 1 ; Int on high level
MOVI L4, 1 << 0 ;
UpdateFCR ; Enable IO1 Interrupt
CMPI L0, -1 ; Overlapped?
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