📄 flashstr.lst
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00000000 B 326 MessageLastPtr EQU 4
00000000 B 327 MessageReceivePtr EQU 8
00000000 B 328 MessageSendPtr EQU 12
00000000 B 329
00000000 B 330 SOFTRESET EQU 0 ; Settin
00000000 B 331 HARDRESET EQU 1
00000000 A 14 include "SAMSUNG.INC"
00000000 B 1 ;=======================================
00000000 B 2 ; Project : Read/Write Programs for
00000000 B 3 ;
00000000 B 4 ; Module : SAMSUNG.INC
00000000 B 5 ;
00000000 B 6 ; Copyright : hyperstone AG
00000000 B 7 ; Line Eid Stra遝 3 ;
00000000 B 8 ; D-78467 Konstanz, German
00000000 B 9 ;
00000000 B 10 ; Date : March 26, 2004
00000000 B 11 ;
00000000 B 12 ;=======================================
00000000 B 13 ; support SAMS4
00000000 B 14 ; 29.08.03 new versions t1024/ft1024, sa
00000000 B 15 ; 18.02.03 for INF3: opcodes INIT_TEST1,
00000000 B 16 ; 26.03.04 HYNIX3-version
00000000 B 17 ;=======================================
00000000 B 18
00000000 B 19 INV_BACKPTR_524 EQU 1
00000000 B 20
00000000 B 21 if INV_BACKPTR_524
00000000 B 22 xref _NumberOfFFBytes
00000000 B 23 endif
00000000 B 24 if defined(INF3)
00000000 B 25 MULTI_PLANE EQU 0
00000000 B 26 MAX_PLANES EQU 1
00000000 B 27 SECTOR_BITS EQU 5
00000000 B 28 BLOCK_NUMBER_BITS EQU 12
00000000 B 29 CHIPNO_SHIFT EQU (BLOCK_NUMBER_BI
00000000 B 30 CHIPNO EQU <(%1111 << CHIPN
00000000 B 31 PAGE_BITS EQU 0
00000000 B 32 PAGE_MASK EQU ((1<<PAGE_BITS)-
00000000 B 33 BLOCK_MASK EQU $ffffffe0
00000000 B 34 endif
00000000 B 35
00000000 B 36 VOLTAGE_MASK EQU (1 << 2)
00000000 B 37 IO1Level EQU (1 << 4)
00000000 B 38 IO3Level EQU (1 << 6) ;
00000000 B 39 ClockDownIO EQU 1<<27 | %1111<<2
00000000 B 40
00000000 B 41
00000000 B 42 ;=======================================
00000000 B 43 ; I/O Timing Definitions
00000000 B 44 ;=======================================
00000000 B 45
Hyperstone Macro Assembler Version 4.26 04-12-01 15:45:21 page: 9
PC Machine Code I Line File: SAMSUNG.INC
00000000 B 46 IO_SETUP_0 EQU (%00 << 8)
00000000 B 47 IO_SETUP_1 EQU (%01 << 8)
00000000 B 48 IO_SETUP_2 EQU (%10 << 8)
00000000 B 49 IO_SETUP_3 EQU (%11 << 8)
00000000 B 50
00000000 B 51 IO_ACCESS_2 EQU (%000 << 5)
00000000 B 52 IO_ACCESS_4 EQU (%001 << 5)
00000000 B 53 IO_ACCESS_6 EQU (%010 << 5)
00000000 B 54 IO_ACCESS_8 EQU (%011 << 5)
00000000 B 55 IO_ACCESS_10 EQU (%100 << 5)
00000000 B 56 IO_ACCESS_12 EQU (%101 << 5)
00000000 B 57 IO_ACCESS_14 EQU (%110 << 5)
00000000 B 58 IO_ACCESS_16 EQU (%111 << 5)
00000000 B 59
00000000 B 60 IO_HOLD_0 EQU (%00 << 3)
00000000 B 61 IO_HOLD_2 EQU (%01 << 3)
00000000 B 62 IO_HOLD_4 EQU (%10 << 3)
00000000 B 63 IO_HOLD_6 EQU (%11 << 3)
00000000 B 64
00000000 B 65 ;=======================================
00000000 B 66 ; Decoder Control via CHORUS Flash Contr
00000000 B 67 ;=======================================
00000000 B 68
00000000 B 69 ECC_TIMING EQU (15<<4)
00000000 B 70 IO_TIMING EQU (15<<4)
00000000 B 71
00000000 B 72 IO_CONTROL EQU (1<<27 | 1<<24 |
00000000 B 73 IO_PCMCIA EQU (1<<27 | 1<<23 |
00000000 B 74 IO_ECC EQU (1<<27 | 1<<22 |
00000000 B 75 IO_SM EQU (1<<27 | 1<<22 |
00000000 B 76
00000000 B 77 ISR_Reg EQU IO_CONTROL | %0
00000000 B 78 MSR_Reg EQU IO_CONTROL | %0
00000000 B 79 TIR_Reg EQU IO_CONTROL | %0
00000000 B 80 PIR_Reg EQU IO_CONTROL | %0
00000000 B 81
00000000 B 82 ATA_Feature EQU IO_PCMCIA | %00
00000000 B 83 ATA_SectCount EQU IO_PCMCIA | %00
00000000 B 84 ATA_SectNumber EQU IO_PCMCIA | %00
00000000 B 85 ATA_CylLow EQU IO_PCMCIA | %01
00000000 B 86 ATA_CylHigh EQU IO_PCMCIA | %01
00000000 B 87 ATA_DriveHead EQU IO_PCMCIA | %01
00000000 B 88 ATA_Command EQU IO_PCMCIA | %01
00000000 B 89 ATA_Status EQU IO_PCMCIA | %10
00000000 B 90 ATA_Error EQU IO_PCMCIA | %10
00000000 B 91 PCM_Config1 EQU IO_PCMCIA | %10
00000000 B 92 PCM_Config2 EQU IO_PCMCIA | %10
00000000 B 93 PCM_Config3 EQU IO_PCMCIA | %11
00000000 B 94 PCM_Config4 EQU IO_PCMCIA | %11
00000000 B 95 ATA_DevCtrl EQU IO_PCMCIA | %11
00000000 B 96 ATA_DrvAddr EQU IO_PCMCIA | %11
00000000 B 97
00000000 B 98 READ_B3_B2 EQU (IO_ECC | (%000
Hyperstone Macro Assembler Version 4.26 04-12-01 15:45:21 page: 10
PC Machine Code I Line File: SAMSUNG.INC
00000000 B 99 READ_B1_B0 EQU (IO_ECC | (%001
00000000 B 100 READ_S3_S2 EQU (IO_ECC | (%010
00000000 B 101 READ_S1_S0 EQU (IO_ECC | (%011
00000000 B 102 RESET_PARITY EQU (IO_ECC | (%000
00000000 B 103 WRITE_S3_S2 EQU (IO_ECC | (%010
00000000 B 104 WRITE_S1_S0 EQU (IO_ECC | (%011
00000000 B 105 READ_FF_COUNTER EQU (IO_ECC | (%100
00000000 B 106 WRITE_FF_COUNTER EQU (IO_ECC | (%100
00000000 B 107 WRITE_INTO_PARITY EQU (IO_ECC | (%101
00000000 B 108 WRITE_INTO_SYNDROM EQU (IO_ECC | (%111
00000000 B 109
00000000 B 110 SM_PARITY_EVEN EQU (IO_SM | (%000 <
00000000 B 111 SM_PARITY_ODD EQU (IO_SM | (%001 <
00000000 B 112 SM_RESET_PARITY EQU (IO_SM | (%000 <
00000000 B 113 SM_LP_LOW EQU (IO_SM | (%100 <
00000000 B 114 SM_LP_HIGH EQU (IO_SM | (%101 <
00000000 B 115 SM_CP EQU (IO_SM | (%110 <
00000000 B 116
00000000 B 117 ;=======================================
00000000 B 118 ; SAMSUNG Flash related definitions
00000000 B 119 ;=======================================
00000000 B 120
00000000 B 121 SAM_BASE_ADDR EQU $800FFFF0 ; Bas
00000000 B 122
00000000 B 123 ifdef MODE_16BIT
00000000 B 125 else
00000000 B 126 B16 EQU 0
00000000 B 127 endif
00000000 B 128 SAM_CLE_BIT EQU (1 << 2) ; CLE
00000000 B 129 SAM_ALE_BIT EQU (1 << 3) ; ALE
00000000 B 130 SAM_SELECT_CHIP0 EQU (1 << 4) ; addr
00000000 B 131
00000000 B 132 ;FLASH_ECC_ENABLE EQU (1 << 20) ; en
00000000 B 133 FLASH_ECC_ENABLE EQU ((1 << 20)|(1 <<
00000000 B 134 FLASH_SM_ENABLE EQU (1 << 24) ; ena
00000000 B 135 FLASH_INHIBIT EQU (1 << 22) ; inh
00000000 B 136 FLASH_IDLE EQU (SAM_BASE_ADDR|FLASH_
00000000 B 137
00000000 B 138 ;=======================================
00000000 B 139 ; Flash Commands
00000000 B 140 ;=======================================
00000000 B 141
00000000 B 142 WRITE_SECTOR EQU $80
00000000 B 143 READ_SECTOR EQU $00
00000000 B 144 READ_SECTOR_MULTIPLANE EQU $03
00000000 B 145 GAPLESSREAD EQU $02
00000000 B 146 SET_PTR_A_AREA EQU $00
00000000 B 147 SET_PTR_B_AREA EQU $01
00000000 B 148 SET_PTR_C_AREA EQU $50
00000000 B 149 READ_ID EQU $90
00000000 B 150 RESET EQU $FF
00000000 B 151 PROGRAM EQU $10
00000000 B 152 PROGRAM_MULTIPLANE EQU $11
Hyperstone Macro Assembler Version 4.26 04-12-01 15:45:21 page: 11
PC Machine Code I Line File: SAMSUNG.INC
00000000 B 153 ERASE1 EQU $60
00000000 B 154 ERASE2 EQU $D0
00000000 B 155 SUSPEND_ERASE EQU $B0
00000000 B 156 RESUME_ERASE EQU $D0
00000000 B 157 READ_STATUS EQU $70
00000000 B 158 READ_CONFIRM EQU $30
00000000 B 159 CACHE_PROGRAM EQU $15
00000000 B 160 RANDOM_DATA_INPUT EQU $85
00000000 B 161 RANDOM_DATA_INPUT4 EQU $8A ; SAMS
00000000 B 162 RANDOM_DATA_OUTPUT EQU $05
00000000 B 163 RANDOM_DATA_OUTPUT1 EQU $E0
00000000 B 164 READ_COPYBACK EQU $00
00000000 B 165 READ_COPYBACK_CONFIRM EQU $35
00000000 B 166 RANDOM_DATA_INPUT1 EQU $85 ; CopyB
00000000 B 167 RANDOM_DATA_INPUT2 EQU $85 ; CopyB
00000000 B 168 SKIP EQU $AB
00000000 B 169 ifdef INF3
00000000 B 170 INIT_TEST1 EQU $5a
00000000 B 171 INIT_TEST2 EQU $56
00000000 B 172 EXIT_TEST EQU $43
00000000 B 173 endif
00000000 B 174
00000000 B 175 MAX_CHIP EQU 16
00000000 B 176 NO_PENDING_WRITE EQU $ff
00000000 B 177 CHIP_SELECT0 EQU (SAM_SELECT
00000000 B 178
00000000 B 179 ;=======================================
00000000 B 180 ; Device hardware independent FlashOpcod
00000000 B 181 ;=======================================
00000000 B 182
00000000 B 183 IDLE_OPC EQU
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