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;============================================================================;
; Project : Read/Write Programs for SAMSUNG Flash Memories ;
; ;
; Module : SAMSUNG.INC ;
; ;
; Copyright : hyperstone AG ;
; Line Eid Stra遝 3 ;
; D-78467 Konstanz, Germany ;
; ;
; Date : March 26, 2004 ;
; ;
;============================================================================;
; support SAMS4
; 29.08.03 new versions t1024/ft1024, sams316/pref316
; 18.02.03 for INF3: opcodes INIT_TEST1, INIT_TEST2, EXIT_TEST
; 26.03.04 HYNIX3-version
;============================================================================;
INV_BACKPTR_524 EQU 1
if INV_BACKPTR_524
xref _NumberOfFFBytes
endif
if defined(INF3)
MULTI_PLANE EQU 0
MAX_PLANES EQU 1
SECTOR_BITS EQU 5
BLOCK_NUMBER_BITS EQU 12
CHIPNO_SHIFT EQU (BLOCK_NUMBER_BITS+SECTOR_BITS)
CHIPNO EQU <(%1111 << CHIPNO_SHIFT)>
PAGE_BITS EQU 0
PAGE_MASK EQU ((1<<PAGE_BITS)-1)
BLOCK_MASK EQU $ffffffe0
endif
VOLTAGE_MASK EQU (1 << 2) ; ISR
IO1Level EQU (1 << 4) ;
IO3Level EQU (1 << 6) ;
ClockDownIO EQU 1<<27 | %1111<<22 | %1111<<4 ; clock down I/O access
;============================================================================;
; I/O Timing Definitions ;
;============================================================================;
IO_SETUP_0 EQU (%00 << 8)
IO_SETUP_1 EQU (%01 << 8)
IO_SETUP_2 EQU (%10 << 8)
IO_SETUP_3 EQU (%11 << 8)
IO_ACCESS_2 EQU (%000 << 5)
IO_ACCESS_4 EQU (%001 << 5)
IO_ACCESS_6 EQU (%010 << 5)
IO_ACCESS_8 EQU (%011 << 5)
IO_ACCESS_10 EQU (%100 << 5)
IO_ACCESS_12 EQU (%101 << 5)
IO_ACCESS_14 EQU (%110 << 5)
IO_ACCESS_16 EQU (%111 << 5)
IO_HOLD_0 EQU (%00 << 3)
IO_HOLD_2 EQU (%01 << 3)
IO_HOLD_4 EQU (%10 << 3)
IO_HOLD_6 EQU (%11 << 3)
;============================================================================;
; Decoder Control via CHORUS Flash Control Logic ;
;============================================================================;
ECC_TIMING EQU (15<<4)
IO_TIMING EQU (15<<4)
IO_CONTROL EQU (1<<27 | 1<<24 | IO_TIMING)
IO_PCMCIA EQU (1<<27 | 1<<23 | IO_TIMING)
IO_ECC EQU (1<<27 | 1<<22 | 0<<16 | ECC_TIMING)
IO_SM EQU (1<<27 | 1<<22 | 1<<16 | ECC_TIMING)
ISR_Reg EQU IO_CONTROL | %0000<<13
MSR_Reg EQU IO_CONTROL | %0001<<13
TIR_Reg EQU IO_CONTROL | %0010<<13
PIR_Reg EQU IO_CONTROL | %0011<<13
ATA_Feature EQU IO_PCMCIA | %0001<<13
ATA_SectCount EQU IO_PCMCIA | %0010<<13
ATA_SectNumber EQU IO_PCMCIA | %0011<<13
ATA_CylLow EQU IO_PCMCIA | %0100<<13
ATA_CylHigh EQU IO_PCMCIA | %0101<<13
ATA_DriveHead EQU IO_PCMCIA | %0110<<13
ATA_Command EQU IO_PCMCIA | %0111<<13
ATA_Status EQU IO_PCMCIA | %1000<<13
ATA_Error EQU IO_PCMCIA | %1001<<13
PCM_Config1 EQU IO_PCMCIA | %1010<<13
PCM_Config2 EQU IO_PCMCIA | %1011<<13
PCM_Config3 EQU IO_PCMCIA | %1100<<13
PCM_Config4 EQU IO_PCMCIA | %1101<<13
ATA_DevCtrl EQU IO_PCMCIA | %1110<<13
ATA_DrvAddr EQU IO_PCMCIA | %1111<<13
READ_B3_B2 EQU (IO_ECC | (%000 << 13)) ; ECC Unit
READ_B1_B0 EQU (IO_ECC | (%001 << 13))
READ_S3_S2 EQU (IO_ECC | (%010 << 13))
READ_S1_S0 EQU (IO_ECC | (%011 << 13))
RESET_PARITY EQU (IO_ECC | (%000 << 13))
WRITE_S3_S2 EQU (IO_ECC | (%010 << 13))
WRITE_S1_S0 EQU (IO_ECC | (%011 << 13))
READ_FF_COUNTER EQU (IO_ECC | (%100 << 13))
WRITE_FF_COUNTER EQU (IO_ECC | (%100 << 13))
WRITE_INTO_PARITY EQU (IO_ECC | (%101 << 13))
WRITE_INTO_SYNDROM EQU (IO_ECC | (%111 << 13))
SM_PARITY_EVEN EQU (IO_SM | (%000 << 13)) ; CRC Unit
SM_PARITY_ODD EQU (IO_SM | (%001 << 13))
SM_RESET_PARITY EQU (IO_SM | (%000 << 13))
SM_LP_LOW EQU (IO_SM | (%100 << 13))
SM_LP_HIGH EQU (IO_SM | (%101 << 13))
SM_CP EQU (IO_SM | (%110 << 13))
;============================================================================;
; SAMSUNG Flash related definitions ;
;============================================================================;
SAM_BASE_ADDR EQU $800FFFF0 ; Base address and CS#
ifdef MODE_16BIT
B16 EQU 1 ; ByteAccess & 16Bit-Mem2
else
B16 EQU 0 ; ByteAccess & 8Bit-Mem2
endif
SAM_CLE_BIT EQU (1 << 2) ; CLE pin
SAM_ALE_BIT EQU (1 << 3) ; ALE pin
SAM_SELECT_CHIP0 EQU (1 << 4) ; address pin for chip0 CS
;FLASH_ECC_ENABLE EQU (1 << 20) ; enable ECC unit
FLASH_ECC_ENABLE EQU ((1 << 20)|(1 << 24)) ; enable ECC & CRC unit
FLASH_SM_ENABLE EQU (1 << 24) ; enable SmartMedia CRC unit
FLASH_INHIBIT EQU (1 << 22) ; inhibit flash access signals
FLASH_IDLE EQU (SAM_BASE_ADDR|FLASH_INHIBIT) ; deselect all flashes
;============================================================================;
; Flash Commands ;
;============================================================================;
WRITE_SECTOR EQU $80
READ_SECTOR EQU $00
READ_SECTOR_MULTIPLANE EQU $03
GAPLESSREAD EQU $02
SET_PTR_A_AREA EQU $00
SET_PTR_B_AREA EQU $01
SET_PTR_C_AREA EQU $50
READ_ID EQU $90
RESET EQU $FF
PROGRAM EQU $10
PROGRAM_MULTIPLANE EQU $11
ERASE1 EQU $60
ERASE2 EQU $D0
SUSPEND_ERASE EQU $B0
RESUME_ERASE EQU $D0
READ_STATUS EQU $70
READ_CONFIRM EQU $30
CACHE_PROGRAM EQU $15
RANDOM_DATA_INPUT EQU $85
RANDOM_DATA_INPUT4 EQU $8A ; SAMS4
RANDOM_DATA_OUTPUT EQU $05
RANDOM_DATA_OUTPUT1 EQU $E0
READ_COPYBACK EQU $00
READ_COPYBACK_CONFIRM EQU $35
RANDOM_DATA_INPUT1 EQU $85 ; CopyBack 1. Sector
RANDOM_DATA_INPUT2 EQU $85 ; CopyBack next Sector
SKIP EQU $AB
ifdef INF3
INIT_TEST1 EQU $5a
INIT_TEST2 EQU $56
EXIT_TEST EQU $43
endif
MAX_CHIP EQU 16
NO_PENDING_WRITE EQU $ff
CHIP_SELECT0 EQU (SAM_SELECT_CHIP0 ^ SAM_BASE_ADDR)
;============================================================================;
; Device hardware independent FlashOpcodes ;
;============================================================================;
IDLE_OPC EQU 0
READ_DEVICE_ID_OPC EQU 1
ERASE_BLOCK_OPC EQU 2
ERASE_BLOCK1_OPC EQU 3
READ_SECTOR_OPC EQU 4
WRITE_SECTOR_OPC EQU 5
PROGRAM_SECTOR_OPC EQU 6
READ_CONFIRM_OPC EQU 7
CACHE_PROGRAM_OPC EQU 8
RANDOM_DATA_INPUT_OPC EQU 9
RANDOM_DATA_OUTPUT_OPC EQU 10
RANDOM_DATA_OUTPUT1_OPC EQU 11
READ_OVERHEAD_OPC EQU 12
READ_OVERHEAD_ECC_OPC EQU 13
WRITE_OVERHEAD_OPC EQU 14
READ_COPYBACK_OPC EQU 15
READ_COPYBACK_CONFIRM_OPC EQU 16
RANDOM_DATA_INPUT1_OPC EQU 17
RANDOM_DATA_INPUT2_OPC EQU 18
PROGRAM_SECTOR_MULTIPLANE_OPC EQU 19
PROGRAM_SECTOR_PARTIALCOPYBACK_OPC EQU 19
READ_SECTOR_MULTIPLANE_OPC EQU 20
READ_SECTOR_PARTIALCOPYBACK_OPC EQU 20
ifdef INF3
INIT_TEST1_OPC EQU 21
INIT_TEST2_OPC EQU 22
EXIT_TEST_OPC EQU 23
MAX_OPC EQU EXIT_TEST_OPC+1
else
MAX_OPC EQU READ_SECTOR_MULTIPLANE_OPC+1
endif
DONT_SAVE_OPC EQU (1<<8) ;
;============================================================================;
; Flags for Write/Erase ;
;============================================================================;
OVERLAPPED EQU (1<<0)
WITH_ECC EQU (1<<1)
WITH_CRC EQU (1<<2)
ERROR_IF_ECC_NEEDED EQU (1<<3)
READ_WRITE_LONG EQU (1<<4)
READ_SKIP_OPC EQU (1<<5)
SKIP_PROGRAM EQU (1<<5)
SKIP_ERASE EQU (1<<5)
SKIP_COPY_PAGE EQU (1<<5)
READ_SKIP_IDLE EQU (1<<6)
WRITE_WORD_ECC EQU (1<<7)
READ_AHEAD EQU (1<<8)
WRITE_OVERHEAD EQU (1<<9)
READ_WRITE_SECURE EQU (1<<10)
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