📄 samsung.asm
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;============================================================================;
; Project : Read/Write Programs for NAND Flash Memories ;
; (HyFlash Controller) ;
; Module : SAMSUNG.ASM ;
; ;
; Copyright : hyperstone AG ;
; Line Eid Stra醗 3 ;
; D-78467 Konstanz, Germany ;
; ;
; Date : March 26, 2004 ;
;============================================================================;
ASSERT EQU 0
include "SYSCONST.INC"
INCLUDE "FLASHSTR.INC"
INCLUDE "SAMSUNG.INC"
if NORTK==0
INCLUDE "MYRTK.INC"
ROM_ACTIVE EQU 0
CMD_LIST EQU 1
CMD_COUNT EQU 0
else
INCLUDE "PCMRTK.INC"
ROM_ACTIVE EQU 1
CMD_LIST EQU 0
CMD_COUNT EQU 0
endif
XDEF _ChipSelectSkipOpcTrapEntry
XDEF _ChipSelectTrapEntry
XDEF _FlashIdleTrapEntry
XDEF _FlashIdle1TrapEntry
XDEF _SetOpcTrapEntry
XDEF _SetAddrTrapEntry
XDEF _PollForReadyTrapEntry
XDEF _ReadStatusTrapEntry
XDEF _ReadWordTrapEntry
XDEF _WriteWordTrapEntry
XDEF _WaitForReadyTrapEntry
XDEF _SetOverlappedTrapEntry
XDEF _WriteChunkTrapEntry
XDEF _ReadChunkTrapEntry
XDEF _ReadDeviceIdTrapEntry
XDEF _SectorToPageTrapEntry
XDEF _NextSectorTrapEntry
XDEF _SetColumnTrapEntry
XDEF _ClearSectorTrapEntry
XDEF _ReadOverheadECC
XDEF _ReadSector
XDEF _ReadSectorFromFlash
XDEF _ReadSectorFromFlashNoECC
XDEF _ReadInvPtrSector
if ROM_ACTIVE==0
XDEF _ReadOverheadFromFlash
XDEF _WriteOverhead
XDEF _EraseBlockRom
XDEF _WriteSector
XDEF _ProgramPage
XDEF _ReadDeviceID
XDEF _EraseOverlapped
XREF _ProgramPageOverlapped
XREF _CmdToFlash
XREF _ReadAddrTab8BitSams5
XREF _CopyPageAddrTab8BitSams5
XREF _WriteAddrTab8BitSams5
XREF _ReadAddrTab8BitSams6
XREF _CopyPageAddrTab8BitSams6
XREF _WriteAddrTab8BitSams6
XREF _ReadAddrTab16BitSams5
XREF _CopyPageAddrTab16BitSams5
XREF _WriteAddrTab16BitSams5
XREF _ReadAddrTab16BitSams6
XREF _CopyPageAddrTab16BitSams6
XREF _WriteAddrTab16BitSams6
XDEF _CopyPageRom
XDEF _PartialCopyPage
XDEF _ReadSectorRom
else
XREF _ReadSectorRom
XREF _ReadInvSectorRom
XREF _ProgramPage
XREF _EraseOverlapped
XREF _ProgramPageOverlapped
XREF _CmdToFlash
XREF _ReadAddrTab8BitSams5
XREF _CopyPageAddrTab8BitSams5
XREF _WriteAddrTab8BitSams5
XREF _ReadAddrTab8BitSams6
XREF _CopyPageAddrTab8BitSams6
XREF _WriteAddrTab8BitSams6
XREF _ReadAddrTab16BitSams5
XREF _CopyPageAddrTab16BitSams5
XREF _WriteAddrTab16BitSams5
XREF _ReadAddrTab16BitSams6
XREF _CopyPageAddrTab16BitSams6
XREF _WriteAddrTab16BitSams6
endif
XDEF _SectorErased
XDEF _ChunkErased
XDEF _ChunkECC
XDEF _DeviceIdAddress
XDEF _DeviceId1
XDEF _DeviceId2
XDEF _DeviceId3
XDEF _ERASE_COUNT
XDEF _FlashState
XDEF _NumberOfAddrBytes
XDEF _ColTab
XREF _ChunkTab
XREF _ChunkTabInvReadOverhead
XDEF _ChunkTabInvRead
XDEF _ChunkTabInvWrite
XREF _correct
XREF _RecalculateCRC
XREF _BitCount
XREF _NumberOfWritePlanes
XREF _NextSectorNumber
XDEF _WaitUntilAllChipsIdle
if NORTK==0
SEGMENT iramtrap
D.WU[128]
endif
SEGMENT code
ifdef INF3
NUMBER_OF_INVPTR_PARTS EQU 2 ; sizeof _InvPtrLengthTab
INV_CHUNK_SIZE EQU 232
endif
OVERHEAD_OFFSET EQU 524
INV_OVERHEAD_OFFSET EQU (INV_CHUNK_SIZE+8)
PHYS_SECTOR_SIZE EQU 528
PHYS_SECTOR_BYTES EQU 528
align 4
_SectorErased:
D.BU[1] 0 ; SectorErased = FALSE
_ChunkErased:
D.BU[1] 0 ;
_ChunkECC: D.BU[1] 0 ;
D.BU[1] 0 ;
_ERASE_COUNT:
D.WU 0
_ERASE_COUNT1:
D.WU[3] 0
_DeviceId1: D.BU[1] 0 ;
_DeviceId2: D.BU[1] 0 ;
_DeviceId3: D.BU[1] 0 ;
_DeviceIdAddress: D.BU[1] 0 ;
_ChunkTabInvWrite:
D.BU[3] INV_CHUNK_SIZE, 0
XDEF _PendingWriteChipNumber
_PendingWriteChipNumber:
D.BU[1] NO_PENDING_WRITE ; max 1 page pending for write
; (powercycle test)
if NUMBER_OF_INVPTR_PARTS == 4
_ChunkTabInvRead:
D.BU[9] INV_CHUNK_SIZE, 8, INV_CHUNK_SIZE, 8, \
INV_CHUNK_SIZE, 8, INV_CHUNK_SIZE, 8,0
endif
if NUMBER_OF_INVPTR_PARTS == 2
_ChunkTabInvRead:
D.BU[5] INV_CHUNK_SIZE, 8, INV_CHUNK_SIZE, 8, 0
endif
if NUMBER_OF_INVPTR_PARTS == 1
_ChunkTabInvRead:
D.BU[3] INV_CHUNK_SIZE, 8, 0
endif
xdef _ActChipNumber2
_ActChipNumber2: ; to actualize ColAddr after read/write
D.HU 0 ; can only optimize, if access succeeding bytes
; without intermediate positioning
xdef _ActChipSelect
_ActChipSelect:
D.WU CHIP_SELECT0; to handle ChipSelect for MultiDie Packages
_ColAddr: D.HU[MAX_CHIP] [MAX_CHIP]0
_FlashState:D.BU[MAX_CHIP] [MAX_CHIP]IDLE_OPC
ifdef INF3
_ColTab: D.HU[MAX_OPC] 0,0,0,0,0,0,0,0,0,0,0,0,OVERHEAD_OFFSET, \
INV_OVERHEAD_OFFSET,OVERHEAD_OFFSET,0,0,0,0,0
_OpcTab: D.BU[MAX_OPC] IDLE_OPC,READ_DEVICE_ID_OPC,ERASE_BLOCK_OPC, \
ERASE_BLOCK1_OPC,READ_SECTOR_OPC,WRITE_SECTOR_OPC,PROGRAM_SECTOR_OPC,\
READ_CONFIRM_OPC,CACHE_PROGRAM_OPC,RANDOM_DATA_INPUT_OPC, \
RANDOM_DATA_OUTPUT_OPC,RANDOM_DATA_OUTPUT1_OPC,READ_SECTOR_OPC, \
READ_SECTOR_OPC,WRITE_SECTOR_OPC,READ_COPYBACK_OPC, \
READ_COPYBACK_CONFIRM_OPC,RANDOM_DATA_INPUT1_OPC,RANDOM_DATA_INPUT2_OPC, \
PROGRAM_SECTOR_MULTIPLANE_OPC,READ_SECTOR_MULTIPLANE_OPC, \
INIT_TEST1_OPC, INIT_TEST2_OPC, EXIT_TEST_OPC
endif
xdef _NumberOfColBytes
ifdef INF3
_FlashOpc: D.BU[MAX_OPC] SKIP,READ_ID,ERASE1,ERASE2, \
READ_SECTOR, WRITE_SECTOR, PROGRAM, \
[2]SKIP, RANDOM_DATA_INPUT, [5]SKIP, \
READ_COPYBACK, SKIP, \
RANDOM_DATA_INPUT4, SKIP, PROGRAM_MULTIPLANE, \
READ_SECTOR_MULTIPLANE, INIT_TEST1, INIT_TEST2, \
EXIT_TEST
_NumberOfColBytes:
D.BU[MAX_OPC] 0,1,0,0, \
1,1,0,[2]0,1,[5]0, \
1,0,1,0,0,1,0,0,0
_NumberOfAddrBytes:
D.BU[MAX_OPC] 0,0,3,0, \
3,3,0,[2]0,3,[5]0, \
3,0,3,0,0,3,1,1,0
endif
if NORTK==0
XDEF _FlashTrap
_FlashTrap: LDHU.N L0, L2, 2 ; Load TrapCode
ADD PC, L2 ; Switch (TrapCode)
ADDI PC, #_ChipSelectTrapEntry-PC ; 00
ADDI PC, #_FlashIdleTrapEntry-PC ; 04
ADDI PC, #_SetOpcTrapEntry-PC ; 08
ADDI PC, #_SetAddrTrapEntry-PC ; 12
ADDI PC, #_PollForReadyTrapEntry-PC ; 16
ADDI PC, #_ReadStatusTrapEntry-PC ; 20
ADDI PC, #_ReadWordTrapEntry-PC ; 24
ADDI PC, #_WriteWordTrapEntry-PC ; 28
ADDI PC, #_WaitForReadyTrapEntry-PC ; 32
ADDI PC, #_SetOverlappedTrapEntry-PC ; 36
ADDI PC, #_WriteChunkTrapEntry-PC ; 40
ADDI PC, #_ReadChunkTrapEntry-PC ; 44
ADDI PC, #_ReadDeviceIdTrapEntry-PC ; 48
ADDI PC, #_SectorToPageTrapEntry-PC ; 52
ADDI PC, #_NextSectorTrapEntry-PC ; 56
ADDI PC, #_ChipSelectSkipOpcTrapEntry-PC ; 60
ADDI PC, #_SetColumnTrapEntry-PC ; 64
ADDI PC, #_ClearSectorTrapEntry-PC ; 68
endif
;============================================================================;
; Function : _WaitUntilAllChipsIdle ;
; ;
; Registers : L0 : Return-PC ;
; L1 : Return-SR ;
; L2 : EventFlags ;
;============================================================================;
_WaitUntilAllChipsIdle:
FRAME L3, L0
ORI SR, LFLAG ; Lock Interrupts for WaitGuard
CMPBI OverlappedFlags, AnyOverlappedEvent; All Chips idle?
BE ExitWaitIdle ; Yes:--> branch
MOVI L2, FlashReadyEvent ; Wait on any Event
ANDN EventFlags, L2 ;
WaitGuard ; until Busy Chips < 4
ExitWaitIdle:
if ASSERT
ANDNI SR, LFLAG
ORI SR, HFLAG
MOV L2, ISR ; Read Input-Status-Register
CMPBI L2, IO1Level ; READY = High ?
TRAPE 60
endif
RET PC, L0
;============================================================================;
; Function : _ChipSelectSkipOpcTrapEntry (TRAP 43) ;
; ;
; Registers : L0 : DeviceIndepOpcode ;
; L1 : alternate ReturnAddress (in), PageNumber (out) ;
; L2 : SectorNumber (in), ChipSelect (out) ;
; L3 : Return-PC ;
; L4 : Return-SR ;
; L5 : ChipNumber ;
; L6 : Temp ;
; L7 : Temp ;
; L8 : Temp ;
;============================================================================;
_ChipSelectSkipOpcTrapEntry:
FRAME L8, L3
MOV L1, L2 ; return ActPage#
MOV L7, L0 ;
ADDI L7, _OpcTab ;
LDBU.D L7, L0, 0 ; Opc = OpcodeTab[Opc]
MASK L5, L1, CHIPNO ; Extract Chip No
SHRI L5, CHIPNO_SHIFT ; Shift ChipNo right
MOVI L2, SAM_SELECT_CHIP0 ; Chip Select bit for Chip 0
SHL L2, L5 ; shift Chip Select
XORI L2, SAM_BASE_ADDR ; and add address bits
XX2 L7, L5, 0 ; Chip# * 2
STHU.D PC, L7, #_ActChipNumber2-PC ; Chip# * 2
ADDI L7, _ColAddr ;
STHU.D L7, 0, 0 ; ColAddr[ActChip#] = 0
if NORTK==0
ORI L4, LFLAG ; LockFlag in Return-SR
endif
RET PC, L3 ;
;============================================================================;
; Function : _ChipSelectTrapEntry (TRAP 39) ;
; ;
; Registers : L0 : DeviceIndepOpcode ;
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