watch.tan.summary

基于quartus II软件 用verilog 语言描述的一个秒表

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.681 ns
From           : display2[0]$latch
To             : display2[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : counter[4]
To             : counter[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : counter[0]
To             : display2[4]$latch
From Clock     : clk
To Clock       : clk
Failed Paths   : 36

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 36

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