aaa3_8.vwf

来自「基于quartus II软件 用verilog 语言描述的38译码器」· VWF 代码 · 共 210 行

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	DATA_OFFSET = 0.0;
	DATA_DURATION = 1000.0;
	SIMULATION_TIME = 0.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("in")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("in[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "in";
}

SIGNAL("in[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "in";
}

SIGNAL("in[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "in";
}

TRANSITION_LIST("in[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 8.199;
		LEVEL 0 FOR 11.4;
		LEVEL 1 FOR 2.199;
		LEVEL 0 FOR 9.6;
		LEVEL 1 FOR 13.199;
		LEVEL 0 FOR 29.799;
		LEVEL 1 FOR 13.999;
		LEVEL 0 FOR 14.799;
		LEVEL 1 FOR 23.399;
		LEVEL 0 FOR 13.999;
		LEVEL 1 FOR 12.098;
		LEVEL 0 FOR 10.32;
		LEVEL 1 FOR 6.799;
		LEVEL 0 FOR 27.199;
		LEVEL 1 FOR 14.599;
		LEVEL 0 FOR 188.069;
		LEVEL 1 FOR 600.324;
	}
}

TRANSITION_LIST("in[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 8.199;
		LEVEL 0 FOR 9.4;
		LEVEL 1 FOR 4.199;
		LEVEL 0 FOR 4.6;
		LEVEL 1 FOR 1.6;
		LEVEL 0 FOR 2.6;
		LEVEL 1 FOR 4.8;
		LEVEL 0 FOR 0.8;
		LEVEL 1 FOR 8.399;
		LEVEL 0 FOR 6.2;
		LEVEL 1 FOR 10.399;
		LEVEL 0 FOR 1.0;
		LEVEL 1 FOR 11.6;
		LEVEL 0 FOR 9.199;
		LEVEL 1 FOR 3.8;
		LEVEL 0 FOR 7.2;
		LEVEL 1 FOR 2.8;
		LEVEL 0 FOR 8.799;
		LEVEL 1 FOR 11.8;
		LEVEL 0 FOR 15.999;
		LEVEL 1 FOR 10.799;
		LEVEL 0 FOR 6.4;
		LEVEL 1 FOR 21.817;
		LEVEL 0 FOR 12.399;
		LEVEL 1 FOR 17.0;
		LEVEL 0 FOR 11.199;
		LEVEL 1 FOR 786.993;
	}
}

TRANSITION_LIST("in[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 8.199;
		LEVEL 0 FOR 5.6;
		LEVEL 1 FOR 7.999;
		LEVEL 0 FOR 14.4;
		LEVEL 1 FOR 8.399;
		LEVEL 0 FOR 17.599;
		LEVEL 1 FOR 6.2;
		LEVEL 0 FOR 4.2;
		LEVEL 1 FOR 2.6;
		LEVEL 0 FOR 5.599;
		LEVEL 1 FOR 10.8;
		LEVEL 0 FOR 4.4;
		LEVEL 1 FOR 15.999;
		LEVEL 0 FOR 13.999;
		LEVEL 1 FOR 17.599;
		LEVEL 0 FOR 11.6;
		LEVEL 1 FOR 10.017;
		LEVEL 0 FOR 17.2;
		LEVEL 1 FOR 20.399;
		LEVEL 0 FOR 13.999;
		LEVEL 1 FOR 783.193;
	}
}

DISPLAY_LINE
{
	CHANNEL = "in";
	EXPAND_STATUS = EXPANDED;
	RADIX = ASCII;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3;
}

DISPLAY_LINE
{
	CHANNEL = "in[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "in[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

TIME_BAR
{
	TIME = 10000;
	MASTER = TRUE;
}
;