aaa3_8.qsf

基于quartus II软件 用verilog 语言描述的38译码器

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		aaa3_8_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY aaa3_8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:43:25  OCTOBER 08, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name VERILOG_FILE aaa3_8.v
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment IOBANK_1 -to in[0]
set_location_assignment IOBANK_2 -to in[1]
set_location_assignment IOBANK_5 -to in[2]
set_location_assignment IOBANK_7 -to out[0]
set_location_assignment PIN_A5 -to out[1]
set_location_assignment PIN_A6 -to out[2]
set_location_assignment PIN_A9 -to out[3]
set_location_assignment PIN_AC20 -to out[4]
set_location_assignment PIN_AC18 -to out[5]
set_location_assignment PIN_AD12 -to out[6]
set_location_assignment PIN_AC5 -to out[7]
set_global_assignment -name VECTOR_WAVEFORM_FILE aaa3_8.vwf
set_global_assignment -name LL_ENABLED ON -section_id aaa3_8
set_global_assignment -name LL_AUTO_SIZE ON -section_id aaa3_8
set_global_assignment -name LL_STATE FLOATING -section_id aaa3_8
set_global_assignment -name LL_RESERVED OFF -section_id aaa3_8
set_global_assignment -name LL_SOFT OFF -section_id aaa3_8
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id aaa3_8
set_global_assignment -name LL_HEIGHT 1 -section_id aaa3_8
set_global_assignment -name LL_WIDTH 1 -section_id aaa3_8
set_global_assignment -name LL_ORIGIN LAB_X1_Y1 -section_id aaa3_8
set_global_assignment -name LL_MEMBER_OF aaa3_8 -section_id aaa3_8
set_global_assignment -name BDF_FILE Block1.bdf