📄 main.lss
字号:
main.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00001f70 00002000 00002000 00002000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000008 40000000 00003f70 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000204 40000008 40000008 00008008 2**2
ALLOC
3 .stack 00000010 40000300 40000300 00008008 2**0
ALLOC
4 .comment 0000015f 00000000 00000000 00008008 2**0
CONTENTS, READONLY
5 .debug_aranges 000000e0 00000000 00000000 00008168 2**3
CONTENTS, READONLY, DEBUGGING
6 .debug_pubnames 00000138 00000000 00000000 00008248 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_info 00000701 00000000 00000000 00008380 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_abbrev 0000023a 00000000 00000000 00008a81 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_line 000002d3 00000000 00000000 00008cbb 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_frame 00000280 00000000 00000000 00008f90 2**2
CONTENTS, READONLY, DEBUGGING
11 .debug_str 00000032 00000000 00000000 00009210 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_loc 000002a0 00000000 00000000 00009242 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00002000 <_boot>:
.func _boot
_boot:
Vectors: LDR PC, Reset_Addr
2000: e59ff018 ldr pc, [pc, #24] ; 2020 <Reset_Addr>
LDR PC, Undef_Addr
2004: e59ff018 ldr pc, [pc, #24] ; 2024 <Undef_Addr>
LDR PC, SWI_Addr
2008: e59ff018 ldr pc, [pc, #24] ; 2028 <SWI_Addr>
LDR PC, PAbt_Addr
200c: e59ff018 ldr pc, [pc, #24] ; 202c <PAbt_Addr>
LDR PC, DAbt_Addr
2010: e59ff018 ldr pc, [pc, #24] ; 2030 <DAbt_Addr>
NOP /* Reserved Vector */
2014: e1a00000 nop (mov r0,r0)
ldr PC, [PC,#-0xFF0] /* VIC Vector jump */
2018: e51ffff0 ldr pc, [pc, #-4080] ; 1030 <USR_Stack_Size+0x830>
LDR PC, FIQ_Addr
201c: e59ff018 ldr pc, [pc, #24] ; 203c <FIQ_Addr>
00002020 <Reset_Addr>:
2020: 00002058 andeq r2, r0, r8, asr r0
00002024 <Undef_Addr>:
2024: 00002040 andeq r2, r0, r0, asr #32
00002028 <SWI_Addr>:
2028: 00002044 andeq r2, r0, r4, asr #32
0000202c <PAbt_Addr>:
202c: 00002048 andeq r2, r0, r8, asr #32
00002030 <DAbt_Addr>:
2030: 0000204c andeq r2, r0, ip, asr #32
2034: 00000000 andeq r0, r0, r0
00002038 <IRQ_Addr>:
2038: 00002050 andeq r2, r0, r0, asr r0
0000203c <FIQ_Addr>:
203c: 00002054 andeq r2, r0, r4, asr r0
00002040 <Undef_Handler>:
Reset_Addr: .word Reset_Handler
Undef_Addr: .word Undef_Handler
SWI_Addr: .word SWI_Handler
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
.word 0 /* Reserved Address */
IRQ_Addr: .word IRQ_Handler
FIQ_Addr: .word FIQ_Handler
Undef_Handler: B Undef_Handler
2040: eafffffe b 2040 <Undef_Handler>
00002044 <SWI_Handler>:
SWI_Handler: B SWI_Handler
2044: eafffffe b 2044 <SWI_Handler>
00002048 <PAbt_Handler>:
PAbt_Handler: B PAbt_Handler
2048: eafffffe b 2048 <PAbt_Handler>
0000204c <DAbt_Handler>:
DAbt_Handler: B DAbt_Handler
204c: eafffffe b 204c <DAbt_Handler>
00002050 <IRQ_Handler>:
IRQ_Handler: B IRQ_Handler
2050: eafffffe b 2050 <IRQ_Handler>
00002054 <FIQ_Handler>:
FIQ_Handler: B FIQ_Handler
2054: eafffffe b 2054 <FIQ_Handler>
00002058 <Reset_Handler>:
Reset_Handler:
# Setup the PLL
LDR R0, =PLL_BASE
2058: e59f00e8 ldr r0, [pc, #232] ; 2148 <.text+0x148>
MOV R1, #0xAA
205c: e3a010aa mov r1, #170 ; 0xaa
MOV R2, #0x55
2060: e3a02055 mov r2, #85 ; 0x55
MOV R3, #PLLCFG_Val
2064: e3a03024 mov r3, #36 ; 0x24
STR R3, [R0, #PLLCFG_OFS]
2068: e5803004 str r3, [r0, #4]
MOV R3, #PLLCON_PLLE
206c: e3a03001 mov r3, #1 ; 0x1
STR R3, [R0, #PLLCON_OFS]
2070: e5803000 str r3, [r0]
STR R1, [R0, #PLLFEED_OFS]
2074: e580100c str r1, [r0, #12]
STR R2, [R0, #PLLFEED_OFS]
2078: e580200c str r2, [r0, #12]
0000207c <PLL_Loop>:
# Wait for pll locked
PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
207c: e5903008 ldr r3, [r0, #8]
ANDS R3, R3, #PLLSTAT_PLOCK
2080: e2133b01 ands r3, r3, #1024 ; 0x400
BEQ PLL_Loop
2084: 0afffffc beq 207c <PLL_Loop>
# Enable PLL output as clock
MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
2088: e3a03003 mov r3, #3 ; 0x3
STR R3, [R0, #PLLCON_OFS]
208c: e5803000 str r3, [r0]
STR R1, [R0, #PLLFEED_OFS]
2090: e580100c str r1, [r0, #12]
STR R2, [R0, #PLLFEED_OFS]
2094: e580200c str r2, [r0, #12]
MOV R1, #VPBDIV_Val
2098: e3a01002 mov r1, #2 ; 0x2
LDR R0,=VPBDIV
209c: e59f00a8 ldr r0, [pc, #168] ; 214c <.text+0x14c>
STR R1,[R0,#0]
20a0: e5801000 str r1, [r0]
# Setup the memory acelerator module
LDR R0, =MAM_BASE
20a4: e59f00a4 ldr r0, [pc, #164] ; 2150 <.text+0x150>
MOV R1, #MAMTIM_Val
20a8: e3a01004 mov r1, #4 ; 0x4
STR R1, [R0, #MAMTIM_OFS]
20ac: e5801004 str r1, [r0, #4]
MOV R1, #MAMCR_Val
20b0: e3a01002 mov r1, #2 ; 0x2
STR R1, [R0, #MAMCR_OFS]
20b4: e5801000 str r1, [r0]
# Setup Stack for each mode
LDR R0, =Top_Stack
20b8: e59f0094 ldr r0, [pc, #148] ; 2154 <.text+0x154>
# Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
20bc: e321f0db msr CPSR_c, #219 ; 0xdb
MOV SP, R0
20c0: e1a0d000 mov sp, r0
SUB R0, R0, #UND_Stack_Size
20c4: e2400004 sub r0, r0, #4 ; 0x4
# Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
20c8: e321f0d7 msr CPSR_c, #215 ; 0xd7
MOV SP, R0
20cc: e1a0d000 mov sp, r0
SUB R0, R0, #ABT_Stack_Size
20d0: e2400004 sub r0, r0, #4 ; 0x4
# Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
20d4: e321f0d1 msr CPSR_c, #209 ; 0xd1
MOV SP, R0
20d8: e1a0d000 mov sp, r0
SUB R0, R0, #FIQ_Stack_Size
20dc: e2400004 sub r0, r0, #4 ; 0x4
# Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
20e0: e321f0d2 msr CPSR_c, #210 ; 0xd2
MOV SP, R0
20e4: e1a0d000 mov sp, r0
SUB R0, R0, #IRQ_Stack_Size
20e8: e2400d06 sub r0, r0, #384 ; 0x180
# Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
20ec: e321f0d3 msr CPSR_c, #211 ; 0xd3
MOV SP, R0
20f0: e1a0d000 mov sp, r0
SUB R0, R0, #SVC_Stack_Size
20f4: e2400004 sub r0, r0, #4 ; 0x4
# Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
20f8: e321f010 msr CPSR_c, #16 ; 0x10
MOV SP, R0
20fc: e1a0d000 mov sp, r0
# Setup a default Stack Limit. useful for "-mapcs-stack-check" gcc option
SUB SL, SP, #USR_Stack_Size
2100: e24dab02 sub sl, sp, #2048 ; 0x800
# Relocate .data section (Copy from ROM to RAM)
LDR R1, =_etext
2104: e59f104c ldr r1, [pc, #76] ; 2158 <.text+0x158>
LDR R2, =_data
2108: e59f204c ldr r2, [pc, #76] ; 215c <.text+0x15c>
LDR R3, =_edata
210c: e59f304c ldr r3, [pc, #76] ; 2160 <.text+0x160>
00002110 <LoopRel>:
LoopRel: CMP R2, R3
2110: e1520003 cmp r2, r3
LDRLO R0, [R1], #4
2114: 34910004 ldrcc r0, [r1], #4
STRLO R0, [R2], #4
2118: 34820004 strcc r0, [r2], #4
BLO LoopRel
211c: 3afffffb bcc 2110 <LoopRel>
# Clear .bss section (Zero init)
MOV R0, #0
2120: e3a00000 mov r0, #0 ; 0x0
LDR R1, =__bss_start__
2124: e59f1038 ldr r1, [pc, #56] ; 2164 <.text+0x164>
LDR R2, =__bss_end__
2128: e59f2038 ldr r2, [pc, #56] ; 2168 <.text+0x168>
0000212c <LoopZI>:
LoopZI: CMP R1, R2
212c: e1510002 cmp r1, r2
STRLO R0, [R1], #4
2130: 34810004 strcc r0, [r1], #4
BLO LoopZI
2134: 3afffffc bcc 212c <LoopZI>
# Jump to C Main code
ADR LR, __main_exit_loop
2138: e28fe004 add lr, pc, #4 ; 0x4
LDR R0, =main
213c: e59f0028 ldr r0, [pc, #40] ; 216c <.text+0x16c>
BX R0
2140: e12fff10 bx r0
00002144 <__main_exit_loop>:
__main_exit_loop: B __main_exit_loop
2144: eafffffe b 2144 <__main_exit_loop>
2148: e01fc080 ands ip, pc, r0, lsl #1
214c: e01fc100 ands ip, pc, r0, lsl #2
2150: e01fc000 ands ip, pc, r0
2154: 40003ff0 strmid r3, [r0], -r0
2158: 00003f70 andeq r3, r0, r0, ror pc
215c: 40000000 andmi r0, r0, r0
2160: 40000008 andmi r0, r0, r8
2164: 40000008 andmi r0, r0, r8
2168: 4000020c andmi r0, r0, ip, lsl #4
216c: 00002334 andeq r2, r0, r4, lsr r3
00002170 <print_banner>:
static unsigned int i;
static unsigned int k;
void print_banner(void)
{
2170: e1a0c00d mov ip, sp
2174: e92dd800 stmdb sp!, {fp, ip, lr, pc}
2178: e24cb004 sub fp, ip, #4 ; 0x4
printf("\n\r");
217c: e59f0024 ldr r0, [pc, #36] ; 21a8 <.text+0x1a8>
2180: eb00070f bl 3dc4 <__printf_from_arm>
printf("http://www.embeddedboards.com micro214x LIS302DL\n\r");
2184: e59f0020 ldr r0, [pc, #32] ; 21ac <.text+0x1ac>
2188: eb00070d bl 3dc4 <__printf_from_arm>
printf("----------------------------------------------------\n\r");
218c: e59f001c ldr r0, [pc, #28] ; 21b0 <.text+0x1b0>
2190: eb00070b bl 3dc4 <__printf_from_arm>
printf("\n\r");
2194: e59f000c ldr r0, [pc, #12] ; 21a8 <.text+0x1a8>
2198: eb000709 bl 3dc4 <__printf_from_arm>
}
219c: e24bd00c sub sp, fp, #12 ; 0xc
21a0: e89d6800 ldmia sp, {fp, sp, lr}
21a4: e12fff1e bx lr
21a8: 00003e0c andeq r3, r0, ip, lsl #28
21ac: 00003e10 andeq r3, r0, r0, lsl lr
21b0: 00003e44 andeq r3, r0, r4, asr #28
000021b4 <initializeAccelerometer>:
void initializeAccelerometer( char range ) {
21b4: e1a0c00d mov ip, sp
21b8: e92dd800 stmdb sp!, {fp, ip, lr, pc}
21bc: e24cb004 sub fp, ip, #4 ; 0x4
21c0: e24dd004 sub sp, sp, #4 ; 0x4
21c4: e1a03000 mov r3, r0
21c8: e54b3010 strb r3, [fp, #-16]
//Initialize the accelerometer
initAccel(range);
21cc: e55b3010 ldrb r3, [fp, #-16]
21d0: e1a00003 mov r0, r3
21d4: eb000086 bl 23f4 <initAccel>
//Set Accel. to Interrupt.
//WriteLis302Register(FF_WU_CFG_1, XHIE | ZHIE | YHIE); //Enable LIS302 Accel. Interrupts
//WriteLis302Register(FF_WU_THS_1, 55); //Set Accelerometer Threshold to ~1G
WriteLis302Register(CLICK_CFG, LIR | Double_X | Double_Y | Double_Z); //Enable LIS302 Click. Interrupts
21d8: e3a00038 mov r0, #56 ; 0x38
21dc: e3a0106a mov r1, #106 ; 0x6a
21e0: eb0000e8 bl 2588 <WriteLis302Register>
WriteLis302Register(CLICK_THSY_X, 0xff );
21e4: e3a0003b mov r0, #59 ; 0x3b
21e8: e3a010ff mov r1, #255 ; 0xff
21ec: eb0000e5 bl 2588 <WriteLis302Register>
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