📄 startup.lst
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1 # 1 "startup.S"
2 # 1 "<built-in>"
1 #
0
0
2 # Copyright (c) 2009 http:#www.embeddedboards.com
3 #
4 # Permission is hereby granted, free of charge, to any person obtaining a copy
5 # of this software and associated documentation files (the "Software"), to deal
6 # in the Software without restriction, including without limitation the rights
7 # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 # copies of the Software, and to permit persons to whom the Software is
9 # furnished to do so, subject to the following conditions:
10 #
11 # The above copyright notice and this permission notice shall be included in
12 # all copies or substantial portions of the Software.
13 #
14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 # THE SOFTWARE.
21 #
22
23
24 /* Configuration */
25
26 # Stack config
27
28 .equ Top_Stack, 0x40003FF0
29 .equ UND_Stack_Size, 0x00000004
30 .equ SVC_Stack_Size, 0x00000004
31 .equ ABT_Stack_Size, 0x00000004
32 .equ FIQ_Stack_Size, 0x00000004
33 .equ IRQ_Stack_Size, 0x00000180
34 .equ USR_Stack_Size, 0x00000800
35
36 # PLL config
37 .equ PLLCFG_Val, 0x00000024 /* mult=5 , div=2 */
38 # VBPDiv Config
39 .equ VPBDIV_Val, 0x00000002 /* VPB = Main clock */
40
41 # MAM config
42 .equ MAMCR_Val, 0x00000002 /* 0- disabled, 1-partially enabled, 2-fully enabled */
43 .equ MAMTIM_Val, 0x00000004
44
45
46
47 /* Definitions */
48
49 .equ Mode_USR, 0x10
50 .equ Mode_FIQ, 0x11
51 .equ Mode_IRQ, 0x12
52 .equ Mode_SVC, 0x13
53 .equ Mode_ABT, 0x17
54 .equ Mode_UND, 0x1B
55 .equ Mode_SYS, 0x1F
56
57 .equ I_Bit, 0x80
58 .equ F_Bit, 0x40
59
60
61 .equ VPBDIV, 0xE01FC100
62
63 .equ PLL_BASE, 0xE01FC080
64 .equ PLLCON_OFS, 0x00
65 .equ PLLCFG_OFS, 0x04
66 .equ PLLSTAT_OFS, 0x08
67 .equ PLLFEED_OFS, 0x0C
68 .equ PLLCON_PLLE, 1
69 .equ PLLCON_PLLC, 2
70 .equ PLLCFG_MSEL, (0x1F<<0)
71 .equ PLLCFG_PSEL, (0x03<<5)
72 .equ PLLSTAT_PLOCK, (1<<10)
73
74
75
76
77 .equ MAM_BASE, 0xE01FC000 /* MAM Base Address */
78 .equ MAMCR_OFS, 0x00 /* MAM Control Offset*/
79 .equ MAMTIM_OFS, 0x04 /* MAM Timing Offset */
80
81
82
83 # Startup code
84
85 .text
86 .arm
87
88
89 .global _boot
90 .func _boot
91 _boot:
92
93
94 0000 18F09FE5 Vectors: LDR PC, Reset_Addr
95 0004 18F09FE5 LDR PC, Undef_Addr
96 0008 18F09FE5 LDR PC, SWI_Addr
97 000c 18F09FE5 LDR PC, PAbt_Addr
98 0010 18F09FE5 LDR PC, DAbt_Addr
99 0014 0000A0E1 NOP /* Reserved Vector */
100 0018 F0FF1FE5 ldr PC, [PC,#-0xFF0] /* VIC Vector jump */
101 001c 18F09FE5 LDR PC, FIQ_Addr
102
103 0020 58000000 Reset_Addr: .word Reset_Handler
104 0024 40000000 Undef_Addr: .word Undef_Handler
105 0028 44000000 SWI_Addr: .word SWI_Handler
106 002c 48000000 PAbt_Addr: .word PAbt_Handler
107 0030 4C000000 DAbt_Addr: .word DAbt_Handler
108 0034 00000000 .word 0 /* Reserved Address */
109 0038 50000000 IRQ_Addr: .word IRQ_Handler
110 003c 54000000 FIQ_Addr: .word FIQ_Handler
111
112 0040 FEFFFFEA Undef_Handler: B Undef_Handler
113 0044 FEFFFFEA SWI_Handler: B SWI_Handler
114 0048 FEFFFFEA PAbt_Handler: B PAbt_Handler
115 004c FEFFFFEA DAbt_Handler: B DAbt_Handler
116 0050 FEFFFFEA IRQ_Handler: B IRQ_Handler
117 0054 FEFFFFEA FIQ_Handler: B FIQ_Handler
118
119
120 Reset_Handler:
121
122 # Setup the PLL
123
124 0058 E8009FE5 LDR R0, =PLL_BASE
125 005c AA10A0E3 MOV R1, #0xAA
126 0060 5520A0E3 MOV R2, #0x55
127
128 0064 2430A0E3 MOV R3, #PLLCFG_Val
129 0068 043080E5 STR R3, [R0, #PLLCFG_OFS]
130 006c 0130A0E3 MOV R3, #PLLCON_PLLE
131 0070 003080E5 STR R3, [R0, #PLLCON_OFS]
132 0074 0C1080E5 STR R1, [R0, #PLLFEED_OFS]
133 0078 0C2080E5 STR R2, [R0, #PLLFEED_OFS]
134
135 # Wait for pll locked
136 007c 083090E5 PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
137 0080 013B13E2 ANDS R3, R3, #PLLSTAT_PLOCK
138 0084 FCFFFF0A BEQ PLL_Loop
139
140 # Enable PLL output as clock
141 0088 0330A0E3 MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
142 008c 003080E5 STR R3, [R0, #PLLCON_OFS]
143 0090 0C1080E5 STR R1, [R0, #PLLFEED_OFS]
144 0094 0C2080E5 STR R2, [R0, #PLLFEED_OFS]
145
146
147 0098 0210A0E3 MOV R1, #VPBDIV_Val
148 009c A8009FE5 LDR R0,=VPBDIV
149 00a0 001080E5 STR R1,[R0,#0]
150
151
152 # Setup the memory acelerator module
153
154 00a4 A4009FE5 LDR R0, =MAM_BASE
155 00a8 0410A0E3 MOV R1, #MAMTIM_Val
156 00ac 041080E5 STR R1, [R0, #MAMTIM_OFS]
157 00b0 0210A0E3 MOV R1, #MAMCR_Val
158 00b4 001080E5 STR R1, [R0, #MAMCR_OFS]
159
160
161 # Setup Stack for each mode
162
163 00b8 94009FE5 LDR R0, =Top_Stack
164
165 # Enter Undefined Instruction Mode and set its Stack Pointer
166 00bc DBF021E3 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
167 00c0 00D0A0E1 MOV SP, R0
168 00c4 040040E2 SUB R0, R0, #UND_Stack_Size
169
170 # Enter Abort Mode and set its Stack Pointer
171 00c8 D7F021E3 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
172 00cc 00D0A0E1 MOV SP, R0
173 00d0 040040E2 SUB R0, R0, #ABT_Stack_Size
174
175 # Enter FIQ Mode and set its Stack Pointer
176 00d4 D1F021E3 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
177 00d8 00D0A0E1 MOV SP, R0
178 00dc 040040E2 SUB R0, R0, #FIQ_Stack_Size
179
180 # Enter IRQ Mode and set its Stack Pointer
181 00e0 D2F021E3 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
182 00e4 00D0A0E1 MOV SP, R0
183 00e8 060D40E2 SUB R0, R0, #IRQ_Stack_Size
184
185 # Enter Supervisor Mode and set its Stack Pointer
186 00ec D3F021E3 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
187 00f0 00D0A0E1 MOV SP, R0
188 00f4 040040E2 SUB R0, R0, #SVC_Stack_Size
189
190 # Enter User Mode and set its Stack Pointer
191 00f8 10F021E3 MSR CPSR_c, #Mode_USR
192 00fc 00D0A0E1 MOV SP, R0
193
194 # Setup a default Stack Limit. useful for "-mapcs-stack-check" gcc option
195 0100 02AB4DE2 SUB SL, SP, #USR_Stack_Size
196
197
198 # Relocate .data section (Copy from ROM to RAM)
199 0104 4C109FE5 LDR R1, =_etext
200 0108 4C209FE5 LDR R2, =_data
201 010c 4C309FE5 LDR R3, =_edata
202 0110 030052E1 LoopRel: CMP R2, R3
203 0114 04009134 LDRLO R0, [R1], #4
204 0118 04008234 STRLO R0, [R2], #4
205 011c FBFFFF3A BLO LoopRel
206
207
208 # Clear .bss section (Zero init)
209 0120 0000A0E3 MOV R0, #0
210 0124 38109FE5 LDR R1, =__bss_start__
211 0128 38209FE5 LDR R2, =__bss_end__
212 012c 020051E1 LoopZI: CMP R1, R2
213 0130 04008134 STRLO R0, [R1], #4
214 0134 FCFFFF3A BLO LoopZI
215
216
217 # Jump to C Main code
218 0138 04E08FE2 ADR LR, __main_exit_loop
219 013c 28009FE5 LDR R0, =main
220 0140 10FF2FE1 BX R0
221
222 0144 FEFFFFEA __main_exit_loop: B __main_exit_loop
223
224
226 .endfunc
227
228
229 0148 80C01FE0 .end
229 00C11FE0
229 00C01FE0
229 F03F0040
229 00000000
DEFINED SYMBOLS
*ABS*:00000000 startup.S
startup.S:28 *ABS*:40003ff0 Top_Stack
startup.S:29 *ABS*:00000004 UND_Stack_Size
startup.S:30 *ABS*:00000004 SVC_Stack_Size
startup.S:31 *ABS*:00000004 ABT_Stack_Size
startup.S:32 *ABS*:00000004 FIQ_Stack_Size
startup.S:33 *ABS*:00000180 IRQ_Stack_Size
startup.S:34 *ABS*:00000800 USR_Stack_Size
startup.S:37 *ABS*:00000024 PLLCFG_Val
startup.S:39 *ABS*:00000002 VPBDIV_Val
startup.S:42 *ABS*:00000002 MAMCR_Val
startup.S:43 *ABS*:00000004 MAMTIM_Val
startup.S:49 *ABS*:00000010 Mode_USR
startup.S:50 *ABS*:00000011 Mode_FIQ
startup.S:51 *ABS*:00000012 Mode_IRQ
startup.S:52 *ABS*:00000013 Mode_SVC
startup.S:53 *ABS*:00000017 Mode_ABT
startup.S:54 *ABS*:0000001b Mode_UND
startup.S:55 *ABS*:0000001f Mode_SYS
startup.S:57 *ABS*:00000080 I_Bit
startup.S:58 *ABS*:00000040 F_Bit
startup.S:61 *ABS*:e01fc100 VPBDIV
startup.S:63 *ABS*:e01fc080 PLL_BASE
startup.S:64 *ABS*:00000000 PLLCON_OFS
startup.S:65 *ABS*:00000004 PLLCFG_OFS
startup.S:66 *ABS*:00000008 PLLSTAT_OFS
startup.S:67 *ABS*:0000000c PLLFEED_OFS
startup.S:68 *ABS*:00000001 PLLCON_PLLE
startup.S:69 *ABS*:00000002 PLLCON_PLLC
startup.S:70 *ABS*:0000001f PLLCFG_MSEL
startup.S:71 *ABS*:00000060 PLLCFG_PSEL
startup.S:72 *ABS*:00000400 PLLSTAT_PLOCK
startup.S:77 *ABS*:e01fc000 MAM_BASE
startup.S:78 *ABS*:00000000 MAMCR_OFS
startup.S:79 *ABS*:00000004 MAMTIM_OFS
startup.S:86 .text:00000000 $a
startup.S:91 .text:00000000 _boot
startup.S:94 .text:00000000 Vectors
startup.S:103 .text:00000020 Reset_Addr
startup.S:104 .text:00000024 Undef_Addr
startup.S:105 .text:00000028 SWI_Addr
startup.S:106 .text:0000002c PAbt_Addr
startup.S:107 .text:00000030 DAbt_Addr
startup.S:110 .text:0000003c FIQ_Addr
startup.S:103 .text:00000020 $d
startup.S:120 .text:00000058 Reset_Handler
startup.S:112 .text:00000040 Undef_Handler
startup.S:113 .text:00000044 SWI_Handler
startup.S:114 .text:00000048 PAbt_Handler
startup.S:115 .text:0000004c DAbt_Handler
startup.S:109 .text:00000038 IRQ_Addr
startup.S:116 .text:00000050 IRQ_Handler
startup.S:117 .text:00000054 FIQ_Handler
startup.S:112 .text:00000040 $a
startup.S:136 .text:0000007c PLL_Loop
startup.S:202 .text:00000110 LoopRel
startup.S:212 .text:0000012c LoopZI
startup.S:222 .text:00000144 __main_exit_loop
startup.S:229 .text:00000148 $d
UNDEFINED SYMBOLS
_etext
_data
_edata
__bss_start__
__bss_end__
main
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