ac51_exe_data.v

Verilog 8051 IP Core for Cyclone II

		ea_base = 16'h0000;
		ea_indx = 8'h00;
	end
	endcase
end	// always comb

assign	effaddr = ea_base + ea_indx;

always @(posedge clk or negedge rst) begin
	if(~rst) begin
		bnk0r0 <= 8'h00;
		bnk0r1 <= 8'h00;
		bnk1r0 <= 8'h00;
		bnk1r1 <= 8'h00;
		bnk2r0 <= 8'h00;
		bnk2r1 <= 8'h00;
		bnk3r0 <= 8'h00;
		bnk3r1 <= 8'h00;
	end
	else begin
		bnk0r0 <= bnk0r0_nxt;
		bnk0r1 <= bnk0r1_nxt;
		bnk1r0 <= bnk1r0_nxt;
		bnk1r1 <= bnk1r1_nxt;
		bnk2r0 <= bnk2r0_nxt;
		bnk2r1 <= bnk2r1_nxt;
		bnk3r0 <= bnk3r0_nxt;
		bnk3r1 <= bnk3r1_nxt;
	end
end	// always

always @(
	pc_mux or pc_r or inst1_r or inst2_r or inst3_r
	or tmp or irdata_i or effaddr
) begin
	case(pc_mux)
	`PCMUX_ABS:
		new_pc = {pc_r[15:11], inst1_r[7:5], inst2_r};
	`PCMUX_LONG:
		new_pc = {inst2_r, inst3_r};
	`PCMUX_POP:
		new_pc = {tmp, irdata_i};
	`PCMUX_EA:
		new_pc = effaddr;
	`PCMUX_INT0:
		new_pc = 16'h0003;
	`PCMUX_INT1:
		new_pc = 16'h000b;
	`PCMUX_INT2:
		new_pc = 16'h0013;
	`PCMUX_INT3:
		new_pc = 16'h001b;
	`PCMUX_INT4:
		new_pc = 16'h0023;
	`PCMUX_INT5:
		new_pc = 16'h002b;
	default:
		new_pc = 16'h0000;
	endcase
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		cur_pc <= 16'h0000;
	else
		cur_pc <= cur_pc_nxt;
end	// always

always @(cur_pc or cpc_mux or pc_r or pc_nxt) begin
	case(cpc_mux)
	`CPCMUX_PCR:
		cur_pc_nxt = pc_r;
	`CPCMUX_PCN:
		cur_pc_nxt = pc_nxt;
	default:
		cur_pc_nxt = cur_pc;
	endcase
end	// always comb

always @(ina_mux or acc or irdata_i or sp) begin
	case(ina_mux)
	`AMUX_ACC:
		ina = acc;
	`AMUX_IDATA:
		ina = irdata_i;
	`AMUX_SP:
		ina = sp;
	default:
		ina = 8'h00;
	endcase
end	// always comb

always @(
	inb_mux or inst2_r or inst3_r
	or irdata_i or b_reg or acc
) begin
	case(inb_mux)
	`BMUX_INST2:
		inb = inst2_r;
	`BMUX_IDATA:
		inb = irdata_i;
	`BMUX_ONE:
		inb = 8'h01;
	`BMUX_BRG:
		inb = b_reg;
	`BMUX_ACC:
		inb = acc;
	`BMUX_INST3:
		inb = inst3_r;
	default:
		inb = 8'h00;
	endcase
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		tmp <= 8'h00;
	else
		tmp <= tmp_nxt;
end	// always

always @(tmp or tmp_mux or outa or irdata_i) begin
	case(tmp_mux)
	`TMUX_OUTA:
		tmp_nxt = outa;
	`TMUX_IDATA:
		tmp_nxt = irdata_i;
	default:
		tmp_nxt = tmp;
	endcase
end	// always comb

assign	tmp_zero = ~(| tmp);

always @(posedge clk or negedge rst) begin
	if(~rst)
		div_tmp <= 16'h0000;
	else
		div_tmp <= div_tmp_o;
end	// always

assign	div_tmp_i = div_tmp;

always @(rs_bits or inst1_r) begin
	rn_addr = {3'b000, rs_bits, inst1_r[2:0]};
end	// always comb

always @(
	rs_bits or inst1_r
	or bnk0r0 or bnk0r1 or bnk1r0 or bnk1r1
	or bnk2r0 or bnk2r1 or bnk3r0 or bnk3r1
) begin
	ri_addr = 8'h00;

	case({rs_bits, inst1_r[0]})
	3'b000:	ri_addr = bnk0r0;
	3'b001:	ri_addr = bnk0r1;
	3'b010:	ri_addr = bnk1r0;
	3'b011:	ri_addr = bnk1r1;
	3'b100:	ri_addr = bnk2r0;
	3'b101:	ri_addr = bnk2r1;
	3'b110:	ri_addr = bnk3r0;
	3'b111:	ri_addr = bnk3r1;
	endcase
end	// always comb

always @(inst2_r) begin
	bit_addr = 8'h00;

	if(inst2_r[7]) begin	// SFR
		bit_addr = {inst2_r[7:3], 3'b000};
	end
	else begin				// 0x20-0x2f
		bit_addr = {4'b0010, inst2_r[6:3]};
	end
end	// always comb

always @(
	ibus_mux or inst2_r or inst3_r
	or rn_addr or ri_addr or bit_addr
	or sp
	or iwd_mux or acc or outa or outb
	or pc_r or irdata_i or cur_pc
) begin
	iaddr = 8'h00;
	idirect = 1'b0;
	irmw = 1'b0;
	iwdata = 8'h00;
	iwen_i = 1'b0;

	case(ibus_mux)
	`IMUX_DRD2: begin
		iaddr = inst2_r;
		idirect = 1'b1;
	end
	`IMUX_DWR2: begin
		iaddr = inst2_r;
		idirect = 1'b1;
		iwen_i = 1'b1;
	end
	`IMUX_RNRD: begin
		iaddr = rn_addr;
	end
	`IMUX_RIRD:	begin
		iaddr = ri_addr;
	end
	`IMUX_BTRD2: begin
		iaddr = bit_addr;
		idirect = 1'b1;
	end
	`IMUX_BTWR2: begin
		iaddr = bit_addr;
		idirect = 1'b1;
		iwen_i = 1'b1;
	end
	`IMUX_RNWR: begin
		iaddr = rn_addr;
		iwen_i = 1'b1;
	end
	`IMUX_RIWR: begin
		iaddr = ri_addr;
		iwen_i = 1'b1;
	end
	`IMUX_OUTA: begin
		iaddr = outa;
		iwen_i = 1'b1;
	end
	`IMUX_SP: begin
		iaddr = sp;
	end
	`IMUX_DWR3: begin
		iaddr = inst3_r;
		idirect = 1'b1;
		iwen_i = 1'b1;
	end
	`IMUX_DRD2RMW: begin
		iaddr = inst2_r;
		idirect = 1'b1;
		irmw = 1'b1;
	end
	`IMUX_BTRD2RMW: begin
		iaddr = bit_addr;
		idirect = 1'b1;
		irmw = 1'b1;
	end
	endcase

	case(iwd_mux)
	`IWDMUX_INST3:
		iwdata = inst3_r;
	`IWDMUX_ACC:
		iwdata = acc;
	`IWDMUX_OUTA:
		iwdata = outa;
	`IWDMUX_INST2:
		iwdata = inst2_r;
	`IWDMUX_PCL:
		iwdata = pc_r[7:0];
	`IWDMUX_PCH:
		iwdata = pc_r[15:8];
	`IWDMUX_IDATA:
		iwdata = irdata_i;
	`IWDMUX_OUTB:
		iwdata = outb;
	`IWDMUX_CPCL:
		iwdata = cur_pc[7:0];
	`IWDMUX_CPCH:
		iwdata = cur_pc[15:8];
	endcase
end	// always comb

always @(
	bnk0r0 or bnk0r1 or bnk1r0 or bnk1r1
	or bnk2r0 or bnk2r1 or bnk3r0 or bnk3r1
	or iwen_i or idirect or iaddr or iwdata
) begin
	bnk0r0_nxt = bnk0r0;
	bnk0r1_nxt = bnk0r1;
	bnk1r0_nxt = bnk1r0;
	bnk1r1_nxt = bnk1r1;
	bnk2r0_nxt = bnk2r0;
	bnk2r1_nxt = bnk2r1;
	bnk3r0_nxt = bnk3r0;
	bnk3r1_nxt = bnk3r1;
	iwen = iwen_i;

	if(iwen_i) begin
		if({iaddr[7:5], iaddr[2:1]} == 5'b00000) begin
			iwen = 1'b0;
			case({iaddr[4:3], iaddr[0]})
			3'b000:	bnk0r0_nxt = iwdata;
			3'b001:	bnk0r1_nxt = iwdata;
			3'b010:	bnk1r0_nxt = iwdata;
			3'b011:	bnk1r1_nxt = iwdata;
			3'b100:	bnk2r0_nxt = iwdata;
			3'b101:	bnk2r1_nxt = iwdata;
			3'b110:	bnk3r0_nxt = iwdata;
			3'b111:	bnk3r1_nxt = iwdata;
			endcase
		end

		if(idirect & iaddr[7]) begin
			iwen = 1'b0;
		end
	end
end	// always comb

always @(
	sp or dptr or ie_reg or ip_reg or psw or acc or b_reg
	or idirect or iwen_i or iaddr or iwdata
) begin
	// default
	sp_nxt2 = sp;
	dptr_nxt2 = dptr;
	ie_nxt2 = ie_reg;
	ip_nxt2 = ip_reg;
	psw_nxt2 = psw;
	acc_nxt2 = acc;
	b_nxt2 = b_reg;
	iowen = 1'b0;

	if(idirect & iwen_i) begin
		if(iaddr[7]) begin
			case(iaddr[6:0])
			7'h01:			// SP
				sp_nxt2 = iwdata;
			7'h02:			// DPL
				dptr_nxt2 = {dptr[15:8], iwdata};
			7'h03:			// DPH
				dptr_nxt2 = {iwdata, dptr[7:0]};
			7'h28:			// IE
				ie_nxt2 = {iwdata[7], iwdata[5:0]};
			7'h38:			// IP
				ip_nxt2 = iwdata[5:0];
			7'h50: begin	// PSW
				psw_nxt2 = iwdata;
			end
			7'h60:			// ACC
				acc_nxt2 = iwdata;
			7'h70:	// B
				b_nxt2 = iwdata;
			default:
				iowen = 1'b1;
			endcase
		end
	end
end	// always comb

assign	ioaddr = iaddr[6:0];
assign	iowdata = iwdata;
assign	iormw = irmw;

always @(posedge clk or negedge rst) begin
	if(~rst) begin
		iaddr_d <= 8'h00;
		idirect_d <= 1'b0;
	end
	else begin
		iaddr_d <= iaddr;
		idirect_d <= idirect;
	end
end	// always

always @(
	irdata or idirect_d or iaddr_d or iordata
	or bnk0r0 or bnk0r1 or bnk1r0 or bnk1r1
	or bnk2r0 or bnk2r1 or bnk3r0 or bnk3r1
	or sp or dptr or ie_reg or ip_reg
	or psw or acc or b_reg or iordata
) begin
	irdata_i = irdata;

	if({iaddr_d[7:5], iaddr_d[2:1]} == 5'b00000) begin
		case({iaddr_d[4:3], iaddr_d[0]})
		3'b000:	irdata_i = bnk0r0;
		3'b001:	irdata_i = bnk0r1;
		3'b010:	irdata_i = bnk1r0;
		3'b011:	irdata_i = bnk1r1;
		3'b100:	irdata_i = bnk2r0;
		3'b101:	irdata_i = bnk2r1;
		3'b110:	irdata_i = bnk3r0;
		3'b111:	irdata_i = bnk3r1;
		endcase
	end

	if(idirect_d) begin
		if(iaddr_d[7]) begin
			case(iaddr_d[6:0])
			7'h01:	// SP
				irdata_i = sp;
			7'h02:	// DPL
				irdata_i = dptr[7:0];
			7'h03:	// DPH
				irdata_i = dptr[15:8];
			7'h28:	// IE
				irdata_i = {ie_reg[6], 1'b0, ie_reg[5:0]};
			7'h38:	// IP
				irdata_i = {2'b00, ip_reg[5:0]};
			7'h50:	// PSW
				irdata_i = psw;
			7'h60:	// ACC
				irdata_i = acc;
			7'h70:	// B
				irdata_i = b_reg;
			default:
				irdata_i = iordata;
			endcase
		end
	end
end	// always comb

always @(inst2_r or irdata_i) begin
	bit_data = 1'b0;

	case(inst2_r[2:0])
	3'b000:	bit_data = irdata_i[0];
	3'b001:	bit_data = irdata_i[1];
	3'b010:	bit_data = irdata_i[2];
	3'b011:	bit_data = irdata_i[3];
	3'b100:	bit_data = irdata_i[4];
	3'b101:	bit_data = irdata_i[5];
	3'b110:	bit_data = irdata_i[6];
	3'b111:	bit_data = irdata_i[7];
	endcase
end	// always comb

always @(pbus_mux or effaddr) begin

	case(pbus_mux)
	`PMUX_RD_EA: begin
		paddr = effaddr;
		pen = 1'b1;
	end
	default: begin
		paddr = 16'h0000;
		pen = 1'b0;
	end
	endcase
end	// always comb

always @(xbus_mux or dptr or p2 or ri_addr or acc) begin
	xaddr = 16'h0000;
	xen = 1'b0;
	xwdata = 8'h00;
	xwen = 1'b0;

	case(xbus_mux)
	`XMUX_DPTR_RD: begin
		xaddr = dptr;
		xen = 1'b1;
	end
	`XMUX_RI_RD: begin
		xaddr = {p2, ri_addr};
		xen = 1'b1;
	end
	`XMUX_DPTR_WR: begin
		xaddr = dptr;
		xen = 1'b1;
		xwdata = acc;
		xwen = 1'b1;
	end
	`XMUX_RI_WR: begin
		xaddr = {p2, ri_addr};
		xen = 1'b1;
		xwdata = acc;
		xwen = 1'b1;
	end
	endcase
end	// always comb

endmodule


// End of ac51_exe_data.v