ac51_exe_data.v

Verilog 8051 IP Core for Cyclone II

//
// ac51_exe_data.v
//
// ac51 microcontroller core
//
// Version 0.6
//
// Copyright 2008, Hideyuki Abe. All rights reserved.
// Distributed under the terms of the MIT License.
//

`include "ac51_defs.v"

module ac51_exe_data(
	clk,
	rst,
	pc_nxt,
	inst1,
	inst2,
	inst3,
	inst1_r,
	inst_ack,
	pc_mux,
	cpc_mux,
	sp_mux,
	dptr_mux,
	new_pc,
	acc_mux,
	acc_zero,
	breg_mux,
	ina_mux,
	inb_mux,
	ina,
	inb,
	div_tmp_i,
	cy_bit,
	ac_bit,
	ov_bit,
	outa,
	outb,
	div_tmp_o,
	new_cy,
	new_ac,
	new_ov,
	tmp_mux,
	tmp_zero,
	bit_data,
	flg_upd,
	ea_mux,
	ibus_mux,
	iwd_mux,
	iaddr,
	iwdata,
	irdata,
	iwen,
	ioaddr,
	iowdata,
	iordata,
	iormw,
	iowen,
	pbus_mux,
	paddr,
	pen,
	prdata,
	xbus_mux,
	xaddr,
	p2,
	xen,
	xwdata,
	xrdata,
	xwen,
	int_pri,
	int_enb
);

input	clk;
input	rst;
input [15:0]	pc_nxt;
input [7:0]	inst1;
input [7:0]	inst2;
input [7:0]	inst3;
output [7:0]	inst1_r;
input	inst_ack;
input [`PCMUX_LEN - 1:0]	pc_mux;
input [`CPCMUX_LEN - 1:0]	cpc_mux;
input [`SPMUX_LEN - 1:0]	sp_mux;
input [`DPMUX_LEN - 1:0]	dptr_mux;
output [15:0]	new_pc;
input [`ACCMUX_LEN - 1:0]	acc_mux;
output	acc_zero;
input [`BRGMUX_LEN - 1:0]	breg_mux;
input [`AMUX_LEN - 1:0]	ina_mux;
input [`BMUX_LEN - 1:0]	inb_mux;
output [7:0]	ina;
output [7:0]	inb;
output [15:0]	div_tmp_i;
output	cy_bit;
output	ac_bit;
output	ov_bit;
input [7:0]	outa;
input [7:0]	outb;
input [15:0]	div_tmp_o;
input	new_cy;
input	new_ac;
input	new_ov;
input [`TMUX_LEN - 1:0]	tmp_mux;
output	tmp_zero;
output	bit_data;
input [2:0]	flg_upd;	// bit0 - ac, bit1 - cy, bit2 - ov
input [`EAMUX_LEN - 1:0]	ea_mux;
input [`IMUX_LEN - 1:0]	ibus_mux;
input [`IWDMUX_LEN - 1:0]	iwd_mux;
output [7:0]	iaddr;
output [7:0]	iwdata;
input [7:0]	irdata;
output	iwen;
output [6:0]	ioaddr;
output [7:0]	iowdata;
input [7:0]	iordata;
output	iormw;
output	iowen;
input [`PMUX_LEN - 1:0]	pbus_mux;
output [15:0]	paddr;
output	pen;
input [7:0]	prdata;
input [`XMUX_LEN - 1:0]	xbus_mux;
output [15:0]	xaddr;
input [7:0]	p2;	// port 2 for Ri-indirect xaddr
output	xen;
output [7:0]	xwdata;
input [7:0]	xrdata;
output	xwen;
output [5:0]	int_pri;
output [5:0]	int_enb;


reg [15:0]	pc_r;
reg [7:0]	inst1_r;
reg [7:0]	inst2_r;
reg [7:0]	inst3_r;

reg [15:0]	new_pc;

reg [15:0]	cur_pc;
reg [15:0]	cur_pc_nxt;

reg [15:0]	ea_base;
reg [15:0]	ea_indx;
wire [15:0]	effaddr;

// internal data area interface
reg [7:0]	iaddr;
reg	idirect;
reg	irmw;
reg [7:0]	iwdata;
reg	iwen;

// sfr area interface
wire [6:0]	ioaddr;
wire [7:0]	iowdata;
wire [7:0]	iordata;
wire	iormw;
reg	iowen;

reg	iwen_i;

// program area interface
reg [15:0]	paddr;
reg	pen;

// ex data area interface
reg [15:0]	xaddr;
reg	xen;
reg [7:0]	xwdata;
reg	xwen;

reg [7:0]	bnk0r0;
reg [7:0]	bnk0r1;
reg [7:0]	bnk1r0;
reg [7:0]	bnk1r1;
reg [7:0]	bnk2r0;
reg [7:0]	bnk2r1;
reg [7:0]	bnk3r0;
reg [7:0]	bnk3r1;
reg [7:0]	bnk0r0_nxt;
reg [7:0]	bnk0r1_nxt;
reg [7:0]	bnk1r0_nxt;
reg [7:0]	bnk1r1_nxt;
reg [7:0]	bnk2r0_nxt;
reg [7:0]	bnk2r1_nxt;
reg [7:0]	bnk3r0_nxt;
reg [7:0]	bnk3r1_nxt;

reg [7:0]	acc;
reg [7:0]	acc_nxt;
reg [7:0]	acc_nxt2;

reg [7:0]	b_reg;
reg [7:0]	b_nxt;
reg [7:0]	b_nxt2;

reg [7:0]	sp;
reg [7:0]	sp_nxt;
reg [7:0]	sp_nxt2;

reg [15:0]	dptr;
reg [15:0]	dptr_nxt;
reg [15:0]	dptr_nxt2;

reg	cy_bit;
reg	ac_bit;
reg	f0_bit;
reg [1:0]	rs_bits;
reg	ov_bit;
reg	p_bit;
wire [7:0]	psw;
reg	cy_nxt;
reg	ac_nxt;
reg	f0_nxt;
reg [1:0]	rs_nxt;
reg	ov_nxt;
reg [7:0]	psw_nxt2;

reg [6:0]	ie_reg;
reg [5:0]	ip_reg;
reg [6:0]	ie_nxt;
reg [5:0]	ip_nxt;
reg [6:0]	ie_nxt2;
reg [5:0]	ip_nxt2;

// ALU interface
reg [7:0]	ina;
reg [7:0]	inb;

// temporary reg
reg [7:0]	tmp;
reg [7:0]	tmp_nxt;

reg [15:0]	div_tmp;

reg	bit_data;

reg [7:0]	rn_addr;
reg [7:0]	ri_addr;
reg [7:0]	bit_addr;

reg [7:0]	iaddr_d;
reg	idirect_d;
reg [7:0]	irdata_i;


always @(posedge clk or negedge rst) begin
	if(~rst) begin
		pc_r <= 16'h0000;
		inst1_r <= 8'h00;
		inst2_r <= 8'h00;
		inst3_r <= 8'h00;
	end
	else if(inst_ack) begin
		pc_r <= pc_nxt;
		inst1_r <= inst1;
		inst2_r <= inst2;
		inst3_r <= inst3;
	end
end	// always

always @(posedge clk or negedge rst) begin
	if(~rst)
		ac_bit <= 1'b0;
	else
		ac_bit <= ac_nxt;
end	// always

always @(psw_nxt2 or flg_upd or new_ac) begin
	ac_nxt = psw_nxt2[6];

	if(flg_upd[0])
		ac_nxt = new_ac;
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		cy_bit <= 1'b0;
	else
		cy_bit <= cy_nxt;
end	// always

always @(psw_nxt2 or flg_upd or new_cy) begin
	cy_nxt = psw_nxt2[7];

	if(flg_upd[1])
		cy_nxt = new_cy;
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		ov_bit <= 1'b0;
	else
		ov_bit <= ov_nxt;
end	// always

always @(psw_nxt2 or flg_upd or new_ov) begin
	ov_nxt = psw_nxt2[2];

	if(flg_upd[2])
		ov_nxt = new_ov;
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		f0_bit <= 1'b0;
	else
		f0_bit <= f0_nxt;
end	// always

always @(psw_nxt2) begin
	f0_nxt = psw_nxt2[5];
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		rs_bits <= 2'b00;
	else
		rs_bits <= rs_nxt;
end	// always

always @(psw_nxt2) begin
	rs_nxt = psw_nxt2[4:3];
end	// always comb

always @(acc) begin
	p_bit = ^acc;
end	// always comb

assign	psw = {cy_bit, ac_bit, f0_bit, rs_bits, ov_bit, 1'b0, p_bit};

always @(posedge clk or negedge rst) begin
	if(~rst)
		ie_reg <= 7'b0000000;
	else
		ie_reg <= ie_nxt;
end	// always

assign	int_enb = {6{ie_reg[6]}} & ie_reg[5:0];

always @(ie_nxt2) begin
	ie_nxt = ie_nxt2;
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		ip_reg <= 6'b00_0000;
	else
		ip_reg <= ip_nxt;
end	// always

assign	int_pri = ip_reg;

always @(ip_nxt2) begin
	ip_nxt = ip_nxt2;
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		acc <= 1'b0;
	else
		acc <= acc_nxt;
end	// always

assign	acc_zero = ~(| acc);

always @(
	acc_nxt2 or acc_mux or irdata_i or outa or outb
	or inst2_r or prdata or xrdata
) begin
	case(acc_mux)
	`ACCMUX_IDATA:
		acc_nxt = irdata_i;
	`ACCMUX_OUTA:
		acc_nxt = outa;
	`ACCMUX_ZERO:
		acc_nxt = 8'h00;
	`ACCMUX_INST2:
		acc_nxt = inst2_r;
	`ACCMUX_PDATA:
		acc_nxt = prdata;
	`ACCMUX_XDATA:
		acc_nxt = xrdata;
	`ACCMUX_OUTB:
		acc_nxt = outb;
	default:
		acc_nxt = acc_nxt2;
	endcase
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		b_reg <= 8'h00;
	else
		b_reg <= b_nxt;
end	// always

always @(b_nxt2 or breg_mux or outa or outb) begin
	case(breg_mux)
	`BRGMUX_OUTB:
		b_nxt = outb;
	`BRGMUX_OUTA:
		b_nxt = outa;
	default:
		b_nxt = b_nxt2;
	endcase
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		sp <= 8'h07;
	else
		sp <= sp_nxt;
end	// always

always @(sp_nxt2 or sp_mux or outa) begin
	case(sp_mux)
	`SPMUX_OUTA:
		sp_nxt = outa;
	default:
		sp_nxt = sp_nxt2;
	endcase
end	// always comb

always @(posedge clk or negedge rst) begin
	if(~rst)
		dptr <= 16'h0000;
	else
		dptr <= dptr_nxt;
end	// always

always @(
	dptr_nxt2 or dptr_mux or inst2_r or inst3_r or effaddr
) begin
	case(dptr_mux)
	`DPMUX_INST23:
		dptr_nxt = {inst2_r, inst3_r};
	`DPMUX_EA:
		dptr_nxt = effaddr;
	default:
		dptr_nxt = dptr_nxt2;
	endcase
end	// always comb

always @(
	ea_mux or dptr or pc_r or acc
	or inst2_r or inst3_r
) begin
	case(ea_mux)
	`EAMUX_INCDPTR: begin
		ea_base = dptr;
		ea_indx = 16'h0001;
	end
	`EAMUX_ADPTR: begin
		ea_base = dptr;
		ea_indx = {8'h00, acc};
	end
	`EAMUX_APC: begin
		ea_base = pc_r;
		ea_indx = {8'h00, acc};
	end
	`EAMUX_REL2: begin
		ea_base = pc_r;
		ea_indx = {{8{inst2_r[7]}}, inst2_r};
	end
	`EAMUX_REL3: begin
		ea_base = pc_r;
		ea_indx = {{8{inst3_r[7]}}, inst3_r};
	end
	default: begin