cyc2_tb.v

Verilog 8051 IP Core for Cyclone II

//
// cyc2_tb.v
//

module cyc2_tb;

reg	clk;
reg [3:0]	key;

always begin
	#20.8 clk = ~clk;
end

initial begin
	clk = 1'b1;
	key = 4'b0000;
	#41.6
	key = 4'b1111;
	#(41.6 * 65536)	;
	$finish;
end

cyc2 cyc2_0(
	.clk24_0(clk),
	.clk24_1(clk),
	.key(key)
);

endmodule

// End of cyc2_tb.v