ac51_exe_ctrl.v

Verilog 8051 IP Core for Cyclone II

				ibus_mux = `IMUX_BTWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOVC_A_ADPTR) begin
			if(pack) begin
				acc_mux = `ACCMUX_PDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				ea_mux = `EAMUX_ADPTR;
				pbus_mux = `PMUX_RD_EA;
			end
		end
		else if(inst1_r == `OPC_SUBB_A_IMM) begin
			op_sel = `ALUOP_SBB;
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_INST2;
			flg_upd = 3'b111;	// update ac, cy, & ov flag
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_SUBB_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_SBB;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_SUBB_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_SBB;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_SUBB_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_SBB;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ORL_C_NBIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BORNOT;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				flg_upd = 3'b010;	// update cy flag
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOV_C_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BMOV;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				flg_upd = 3'b010;	// update cy flag
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_INC_DPTR) begin
			ea_mux = `EAMUX_INCDPTR;
			dptr_mux = `DPMUX_EA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MUL_AB) begin
			op_sel = `ALUOP_MUL;
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_BRG;
			flg_upd = 3'b110;	// update cy & ov flag
			acc_mux = `ACCMUX_OUTA;
			breg_mux = `BRGMUX_OUTB;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == 8'b1010_0101) begin	// ESC
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r[7:1] == `OPC_MOV_RI_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_RIWR;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_MOV_RN_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_RNWR;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ANL_C_NBIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BANDNOT;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				flg_upd = 3'b010;	// update cy flag
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_CPL_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BCOM;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				ibus_mux = `IMUX_BTWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_CPL_C) begin
			op_sel = `ALUOP_BCOM;
			flg_upd = 3'b010;	// update cy flag
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_CJNE_A_IMM) begin
			if(state == `EST_EXE1) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_INST2;
				tmp_mux = `TMUX_OUTA;
				flg_upd = 3'b010;	// update cy flag
				state_nxt = `EST_EXE2;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r == `OPC_CJNE_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				tmp_mux = `TMUX_OUTA;
				flg_upd = 3'b010;	// update cy flag
				state_nxt = `EST_EXE3;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r[7:1] == `OPC_CJNE_RI_IMM) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				tmp_mux = `TMUX_OUTA;
				flg_upd = 3'b010;	// update cy flag
				state_nxt = `EST_EXE3;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r[7:3] == `OPC_CJNE_RN_IMM) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				tmp_mux = `TMUX_OUTA;
				flg_upd = 3'b010;	// update cy flag
				state_nxt = `EST_EXE3;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r == `OPC_PUSH_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADD;
				ina_mux = `AMUX_SP;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_OUTA;
				iwd_mux = `IWDMUX_IDATA;
				sp_mux = `SPMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_CLR_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BCLR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				ibus_mux = `IMUX_BTWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_CLR_C) begin
			op_sel = `ALUOP_BCLR;
			flg_upd = 3'b010;	// update cy flag
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_SWAP_A) begin
			op_sel = `ALUOP_SWP;
			ina_mux = `AMUX_ACC;
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_XCH_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_ACC;
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_XCH_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_RIWR;
				iwd_mux = `IWDMUX_ACC;
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_XCH_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_RNWR;
				iwd_mux = `IWDMUX_ACC;
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_POP_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_SP;
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_SP;
				inb_mux = `BMUX_ONE;
				sp_mux = `SPMUX_OUTA;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_SETB_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BSET;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				ibus_mux = `IMUX_BTWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_SETB_C) begin
			op_sel = `ALUOP_BSET;
			flg_upd = 3'b010;	// update cy flag
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_DA_A) begin
			op_sel = `ALUOP_DAA;
			ina_mux = `AMUX_ACC;
			flg_upd = 3'b010;	// update cy flag
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_DJNZ_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				tmp_mux = `TMUX_OUTA;
				state_nxt = `EST_EXE3;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r[7:1] == `OPC_XCHD_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XCHD;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				ibus_mux = `IMUX_RIWR;
				iwd_mux = `IWDMUX_OUTB;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_DJNZ_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_RNWR;
				iwd_mux = `IWDMUX_OUTA;
				tmp_mux = `TMUX_OUTA;
				state_nxt = `EST_EXE3;
			end
			else begin
				if(~tmp_zero) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL2;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r == `OPC_MOVX_A_DPTR) begin
			if(xack) begin
				acc_mux = `ACCMUX_XDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				xbus_mux = `XMUX_DPTR_RD;
			end
		end
		else if(inst1_r[7:1] == `OPC_MOVX_A_RI) begin
			if(xack) begin
				acc_mux = `ACCMUX_XDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				xbus_mux = `XMUX_RI_RD;
			end
		end
		else if(inst1_r == `OPC_CLR_A) begin
			acc_mux = `ACCMUX_ZERO;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MOV_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_MOV_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_MOV_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				acc_mux = `ACCMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOVX_DPTR_A) begin
			if(xack) begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				xbus_mux = `XMUX_DPTR_WR;
			end
		end
		else if(inst1_r[7:1] == `OPC_MOVX_RI_A) begin
			if(xack) begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				xbus_mux = `XMUX_RI_WR;
			end
		end
		else if(inst1_r == `OPC_CPL_A) begin
			op_sel = `ALUOP_COM;
			ina_mux = `AMUX_ACC;
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MOV_DIR_A) begin
			ibus_mux = `IMUX_DWR2;
			iwd_mux = `IWDMUX_ACC;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r[7:1] == `OPC_MOV_RI_A) begin
			ibus_mux = `IMUX_RIWR;
			iwd_mux = `IWDMUX_ACC;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r[7:3] == `OPC_MOV_RN_A) begin
			ibus_mux = `IMUX_RNWR;
			iwd_mux = `IWDMUX_ACC;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
	end
end	// always comb


endmodule

// End of ac51_exe_ctrl.v