ac51_exe_ctrl.v

Verilog 8051 IP Core for Cyclone II

				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_ADD_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADD;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_ADD_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADD;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JNB_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				if(~bit_data) begin
					jmp_req = 1'b1;
					ea_mux = `EAMUX_REL3;
					pc_mux = `PCMUX_EA;
					if(jmp_ack) state_nxt = `EST_IDLE;
				end
				else begin
					inst_req = 1'b1;
					if(inst_rdy) state_nxt = `EST_EXE1;
					else state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r == `OPC_RETI) begin
			if(state == `EST_EXE1) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_SP;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_SP;
				sp_mux = `SPMUX_OUTA;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_SP;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_SP;
				tmp_mux = `TMUX_IDATA;
				state_nxt = `EST_EXE3;
			end
			else begin
				op_sel = `ALUOP_SUB;
				ina_mux = `AMUX_SP;
				inb_mux = `BMUX_ONE;
				ibus_mux = `IMUX_SP;
				jmp_req = 1'b1;
				pc_mux = `PCMUX_POP;
				if(jmp_ack) begin
					sp_mux = `SPMUX_OUTA;
					int_state_pop = 1'b1;
					state_nxt = `EST_IDLE;
				end
			end
		end
		else if(inst1_r == `OPC_RLCA) begin
			op_sel = `ALUOP_RLC;
			ina_mux = `AMUX_ACC;
			flg_upd = 3'b010;	// update cy flag
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_ADC_A_IMM) begin
			op_sel = `ALUOP_ADC;
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_INST2;
			flg_upd = 3'b111;	// update ac, cy, & ov flag
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_ADC_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADC;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_ADC_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADC;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_ADC_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_ADC;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				flg_upd = 3'b111;	// update ac, cy, & ov flag
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JC) begin
			if(cy_bit) begin
				jmp_req = 1'b1;
				ea_mux = `EAMUX_REL2;
				pc_mux = `PCMUX_EA;
				if(jmp_ack) state_nxt = `EST_IDLE;
			end
			else begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ORL_DIR_A) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_OR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_ACC;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ORL_DIR_IMM) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_OR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST3;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ORL_A_IMM) begin
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_INST2;
			op_sel = `ALUOP_OR;
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_ORL_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_OR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_ORL_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_OR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_ORL_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_OR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JNC) begin
			if(~cy_bit) begin
				jmp_req = 1'b1;
				ea_mux = `EAMUX_REL2;
				pc_mux = `PCMUX_EA;
				if(jmp_ack) state_nxt = `EST_IDLE;
			end
			else begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ANL_DIR_A) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_AND;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_ACC;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ANL_DIR_IMM) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_AND;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST3;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ANL_A_IMM) begin
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_INST2;
			op_sel = `ALUOP_AND;
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_ANL_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_AND;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_ANL_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_AND;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_ANL_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_AND;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JZ) begin
			if(acc_zero) begin
				jmp_req = 1'b1;
				ea_mux = `EAMUX_REL2;
				pc_mux = `PCMUX_EA;
				if(jmp_ack) state_nxt = `EST_IDLE;
			end
			else begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_XRL_DIR_A) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XOR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_ACC;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_XRL_DIR_IMM) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XOR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST3;
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_XRL_A_IMM) begin
			ina_mux = `AMUX_ACC;
			inb_mux = `BMUX_INST2;
			op_sel = `ALUOP_XOR;
			acc_mux = `ACCMUX_OUTA;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_XRL_A_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XOR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_XRL_A_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XOR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_XRL_A_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_XOR;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_IDATA;
				acc_mux = `ACCMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JNZ) begin
			if(~acc_zero) begin
				jmp_req = 1'b1;
				ea_mux = `EAMUX_REL2;
				pc_mux = `PCMUX_EA;
				if(jmp_ack) state_nxt = `EST_IDLE;
			end
			else begin
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_ORL_C_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BOR;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				flg_upd = 3'b010;	// update cy flag
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_JMP_ADPTR) begin
			jmp_req = 1'b1;
			ea_mux = `EAMUX_ADPTR;
			pc_mux = `PCMUX_EA;
			if(jmp_ack) state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MOV_A_IMM) begin
			acc_mux = `ACCMUX_INST2;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MOV_DIR_IMM) begin
			ibus_mux = `IMUX_DWR2;
			iwd_mux = `IWDMUX_INST3;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r[7:1] == `OPC_MOV_RI_IMM) begin
			ibus_mux = `IMUX_RIWR;
			iwd_mux = `IWDMUX_INST2;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r[7:3] == `OPC_MOV_RN_IMM) begin
			ibus_mux = `IMUX_RNWR;
			iwd_mux = `IWDMUX_INST2;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_SJMP) begin
			jmp_req = 1'b1;
			ea_mux = `EAMUX_REL2;
			pc_mux = `PCMUX_EA;
			if(jmp_ack) state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_ANL_C_BIT) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BAND;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;
				flg_upd = 3'b010;	// update cy flag
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOVC_A_APC) begin
			if(pack) begin
				acc_mux = `ACCMUX_PDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
			else begin
				ea_mux = `EAMUX_APC;
				pbus_mux = `PMUX_RD_EA;
			end
		end
		else if(inst1_r == `OPC_DIV_AB) begin
			if(state == `EST_EXE1) begin
				op_sel = `ALUOP_DIV0;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_BRG;
				flg_upd = 3'b110;	// update cy & ov flag
				acc_mux = `ACCMUX_OUTA;
				breg_mux = `BRGMUX_OUTB;
				div_start = 1'b1;
				state_nxt = `EST_EXE2;
			end
			else if(state == `EST_EXE2) begin
				op_sel = `ALUOP_DIV1;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_BRG;
				flg_upd = 3'b110;	// update cy & ov flag
				acc_mux = `ACCMUX_OUTA;
				breg_mux = `BRGMUX_OUTB;
				if(div_end) state_nxt = `EST_EXE3;
				else state_nxt = state;
			end
			else begin
				op_sel = `ALUOP_DIV1;
				ina_mux = `AMUX_ACC;
				inb_mux = `BMUX_BRG;
				flg_upd = 3'b110;	// update cy & ov flag
				acc_mux = `ACCMUX_OUTB;
				breg_mux = `BRGMUX_OUTA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOV_DIR_DIR) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_DRD2;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_DWR3;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:1] == `OPC_MOV_DIR_RI) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RIRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r[7:3] == `OPC_MOV_DIR_RN) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_RNRD;
				state_nxt = `EST_EXE2;
			end
			else begin
				ibus_mux = `IMUX_DWR2;
				iwd_mux = `IWDMUX_IDATA;
				inst_req = 1'b1;
				if(inst_rdy) state_nxt = `EST_EXE1;
				else state_nxt = `EST_IDLE;
			end
		end
		else if(inst1_r == `OPC_MOV_DPTR_IMM) begin
			dptr_mux = `DPMUX_INST23;
			inst_req = 1'b1;
			if(inst_rdy) state_nxt = `EST_EXE1;
			else state_nxt = `EST_IDLE;
		end
		else if(inst1_r == `OPC_MOV_BIT_C) begin
			if(state == `EST_EXE1) begin
				ibus_mux = `IMUX_BTRD2RMW;
				state_nxt = `EST_EXE2;
			end
			else begin
				op_sel = `ALUOP_BMOV;
				ina_mux = `AMUX_IDATA;
				inb_mux = `BMUX_INST2;