📄 xe1205driver.h
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/*******************************************************************
** File : XE1205driver.h **
********************************************************************
** **
** Version : V 1.0 **
** **
** Written by : Miguel Luis & Gr間oire Guye **
** **
** Date : 19-01-2004 **
** **
** Project : API-1205 **
** **
********************************************************************
** Changes : V 2.1 / MiL - 24-04-2004 **
** **
** : V 2.2 / MiL - 30-07-2004 **
** - Removed workaround for RX/TX switch FIFO clear **
** (chip correction) **
** **
** Changes : V 2.3 / CRo - 06-06-2006 **
** - I/O Ports Definitions section updated **
** **
** Changes : V 2.4 / CRo - 09-01-2007 **
** - No change **
** **
** **
********************************************************************
** Description : XE1205 transceiver drivers Implementation for the**
** XE8000 family products (1205 buffered mode) **
*******************************************************************/
#ifndef __XE1205DRIVER__
#define __XE1205DRIVER__
/*******************************************************************
** Include files **
*******************************************************************/
#include "Globals.h"
/*******************************************************************
** Global definitions **
*******************************************************************/
/*******************************************************************
** RF packet definition **
*******************************************************************/
#define RF_BUFFER_SIZE_MAX 64
#define RF_BUFFER_SIZE 64
#define SYNC_BYTE_FREQ 4
/*******************************************************************
** RF State machine **
*******************************************************************/
#define RF_STOP 0x01
#define RF_BUSY 0x02
#define RF_RX_DONE 0x04
#define RF_TX_DONE 0x08
#define RF_ERROR 0x10
#define RF_TIMEOUT 0x20
#define RF_AFC_DONE 0x40
/*******************************************************************
** RF function return codes **
*******************************************************************/
#define OK 0x00
#define ERROR 0x01
#define RX_TIMEOUT 0x02
#define RX_RUNNING 0x03
#define TX_TIMEOUT 0x04
#define TX_RUNNING 0x05
/*******************************************************************
** I/O Ports Definitions **
*******************************************************************/
#if defined(_XE88LC01A_) || defined(_XE88LC05A_)
#define PORTO RegPCOut
#define PORTI RegPCIn
#define PORTDIR RegPCDir
#define PORTP RegPCPullup
#define ANT_SWITCH RegPCOut
#endif
#if defined(_XE88LC02_) || defined(_XE88LC02_4KI_) || defined(_XE88LC02_8KI_)
#define PORTO RegPD1Out
#define PORTI RegPD1In
#define PORTDIR RegPD1Dir
#define PORTP RegPD1Pullup
#define ANT_SWITCH RegPD1Out
#endif
#if defined(_XE88LC06A_) || defined(_XE88LC07A_)
#define PORTO RegPDOut
#define PORTI RegPDIn
#define PORTDIR RegPDDir
#define PORTP RegPDPullup
#define ANT_SWITCH RegPDOut
#endif
/*******************************************************************
** Port A pins definitions **
********************************************************************
** * uC * XE1205 * PAx **
*******************************************************************/
#define IRQ_1 0x02 //* In * Out * PA1
#define IRQ_0 0x04 //* In * Out * PA2
/*******************************************************************
** Port B pins definitions **
********************************************************************
** * uC * XE1205 * PBx **
*******************************************************************/
/*******************************************************************
** Port C pins definitions **
********************************************************************
** * uC * XE1205 * PCx **
*******************************************************************/
#define NSS_DATA 0x01 //* Out * In * PC0
#define NSS_CONFIG 0x02 //* Out * In * PC1
#define SCK 0x04 //* Out * In * PC2
#define MOSI 0x08 //* Out * In * PC3
#define MISO 0x10 //* In * Out * PC4
#define SW1 0x20 //* Out * In * PC5 // Tx
#define SW0 0x40 //* Out * In * PC6 // Rx
/*******************************************************************
** XE1205 SPI Macros definitions **
*******************************************************************/
#define SPIInit() (PORTDIR = (PORTDIR | SCK | NSS_DATA | NSS_CONFIG | MOSI) & (~(MISO | SW1 | SW0)))
#define SPIClock(level) ((level) ? (PORTO |= SCK) : (PORTO &= ~SCK))
#define SPIMosi(level) ((level) ? (PORTO |= MOSI) : (PORTO &= ~MOSI))
#define SPINssData(level) ((level) ? (PORTO |= NSS_DATA) : (PORTO &= ~NSS_DATA))
#define SPINssConfig(level) ((level) ? (PORTO |= NSS_CONFIG) : (PORTO &= ~NSS_CONFIG))
#define SPIMisoTest() (PORTI & MISO)
/*******************************************************************
** XE1205 definitions **
*******************************************************************/
/*******************************************************************
** XE1205 Operating modes definition **
*******************************************************************/
#define RF_SLEEP 0x00
#define RF_RECEIVER 0x40
#define RF_TRANSMITTER 0x80
#define RF_STANDBY 0xC0
/*******************************************************************
** XE1205 Internal registers Address **
*******************************************************************/
#define REG_MCPARAM1 0x00
#define REG_MCPARAM2 0x01
#define REG_MCPARAM3 0x02
#define REG_MCPARAM4 0x03
#define REG_MCPARAM5 0x04
#define REG_IRQPARAM1 0x05
#define REG_IRQPARAM2 0x06
#define REG_TXPARAM1 0x07
#define REG_RXPARAM1 0x08
#define REG_RXPARAM2 0x09
#define REG_RXPARAM3 0x0A
#define REG_RXPARAM4 0x0B // MSB FEI
#define REG_RXPARAM5 0x0C // LSB FEI
#define REG_RXPARAM6 0x0D // Pattern 1
#define REG_RXPARAM7 0x0E // Pattern 2
#define REG_RXPARAM8 0x0F // Pattern 3
#define REG_RXPARAM9 0x10 // Pattern 4
#define REG_OSCPARAM1 0x11
#define REG_OSCPARAM2 0x12
/*******************************************************************
** XE1205 default register values definition **
*******************************************************************/
#define DEF_MCPARAM1 0x00 //
#define DEF_MCPARAM2 0x00 //
#define DEF_MCPARAM3 0x00 //
#define DEF_MCPARAM4 0x00 //
#define DEF_MCPARAM5 0x00 //
#define DEF_IRQPARAM1 0x00 //
#define DEF_IRQPARAM2 0x00 //
#define DEF_TXPARAM1 0x00 //
#define DEF_RXPARAM1 0x00 //
#define DEF_RXPARAM2 0x00 //
#define DEF_RXPARAM3 0x00 //
#define DEF_RXPARAM4 0x00 // MSB FEI
#define DEF_RXPARAM5 0x00 // MSB FEI
#define DEF_RXPARAM6 0x00 // Pattern 1
#define DEF_RXPARAM7 0x00 // Pattern 2
#define DEF_RXPARAM8 0x00 // Pattern 3
#define DEF_RXPARAM9 0x00 // Pattern 4
#define DEF_OSCPARAM1 0x00 //
#define DEF_OSCPARAM2 0x00 //
/*******************************************************************
** XE1205 bit control definition **
*******************************************************************/
// MC Param 1
// Chip operating mode
#define RF_MC1_STANDBY 0xC0
#define RF_MC1_TRANSMITTER 0x80
#define RF_MC1_RECEIVER 0x40
#define RF_MC1_SLEEP 0x00
// Chip mode selection
#define RF_MC1_MODE_SW_PIN 0x20
#define RF_MC1_MODE_CHIP 0x00
// Enables buffered mode
#define RF_MC1_BUFFERED_MODE_ON 0x10
#define RF_MC1_BUFFERED_MODE_OFF 0x00
// Configure data pin behavior
#define RF_MC1_DATA_UNIDIR_ON 0x08
#define RF_MC1_DATA_UNIDIR_OFF 0x00
// Frequency band
#define RF_MC1_BAND_915 0x06
#define RF_MC1_BAND_868 0x04
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