📄 nonlinear1.mdl
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ShowName on
}
BlockParameterDefaults {
Block {
BlockType Abs
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
}
Block {
BlockType DataTypeConversion
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
SampleTime "-1"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType Signum
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Stop
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "nonlinear1"
Location [438, 155, 1001, 448]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Abs
Name "Abs"
Position [135, 190, 165, 220]
SaturateOnIntegerOverflow off
}
Block {
BlockType Abs
Name "Abs1"
Position [135, 245, 165, 275]
SaturateOnIntegerOverflow off
}
Block {
BlockType Clock
Name "Clock"
Position [25, 30, 45, 50]
Decimation "10"
}
Block {
BlockType Constant
Name "Constant"
Position [295, 185, 325, 215]
Value "0.01"
}
Block {
BlockType Display
Name "Display"
Ports [1]
Position [415, 25, 505, 55]
FontSize 10
Decimation "1"
Lockdown off
}
Block {
BlockType Gain
Name "G1"
Position [205, 105, 235, 135]
Gain "1/6"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "x''"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [275, 105, 305, 135]
IgnoreLimit off
Port {
PortNumber 1
Name "x'"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Integrator
Name "Integrator1"
Ports [1, 1]
Position [370, 105, 400, 135]
InitialCondition "1"
IgnoreLimit off
Port {
PortNumber 1
Name "x"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [355, 212, 385, 243]
InputSameDT off
LogicOutDataTypeMode "Boolean"
}
Block {
BlockType Signum
Name "Sign"
Position [135, 105, 165, 135]
Port {
PortNumber 1
Name "F"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Stop
Name "Stop Simulation"
Position [470, 212, 505, 248]
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [70, 110, 90, 130]
ShowName off
IconShape "round"
Inputs "-|-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [220, 225, 240, 245]
ShowName off
IconShape "round"
Inputs "+|+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "XY Graph"
Ports [2]
Position [475, 110, 505, 145]
SourceBlock "simulink/Sinks/XY Graph"
SourceType "XY scope."
ShowPortLabels on
xmin "-0.5"
xmax "1.5"
ymin "-1"
ymax "0.5"
st "-1"
}
Line {
SrcBlock "Sum"
SrcPort 1
Points [25, 0]
DstBlock "Sign"
DstPort 1
}
Line {
Name "F"
Labels [0, 0]
SrcBlock "Sign"
SrcPort 1
Points [20, 0]
DstBlock "G1"
DstPort 1
}
Line {
Name "x''"
Labels [0, 0]
SrcBlock "G1"
SrcPort 1
Points [0, 0]
DstBlock "Integrator"
DstPort 1
}
Line {
Name "x'"
Labels [0, 0]
SrcBlock "Integrator"
SrcPort 1
Points [0, 0; 25, 0]
Branch {
DstBlock "Integrator1"
DstPort 1
}
Branch {
Points [0, 55]
Branch {
Points [125, 0]
DstBlock "XY Graph"
DstPort 2
}
Branch {
Points [-255, 0]
Branch {
DstBlock "Sum"
DstPort 2
}
Branch {
Labels [2, 0]
Points [0, 30]
DstBlock "Abs"
DstPort 1
}
}
}
}
Line {
Name "x"
Labels [0, 0]
SrcBlock "Integrator1"
SrcPort 1
Points [0, 0; 25, 0]
Branch {
DstBlock "XY Graph"
DstPort 1
}
Branch {
Points [0, -45; -350, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Labels [3, 0]
Points [-45, 0; 0, 185]
DstBlock "Abs1"
DstPort 1
}
}
}
Line {
Labels [0, 0]
SrcBlock "Abs"
SrcPort 1
Points [60, 0]
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Abs1"
SrcPort 1
Points [0, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [95, 0]
DstBlock "Relational\nOperator"
DstPort 2
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [0, 20]
DstBlock "Relational\nOperator"
DstPort 1
}
Line {
SrcBlock "Relational\nOperator"
SrcPort 1
Points [0, 0]
DstBlock "Stop Simulation"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
DstBlock "Display"
DstPort 1
}
}
}
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