📄 arch-ia64.h
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unsigned long fir; unsigned long fdr; unsigned long rsv4; unsigned long ccv; /* 32 */ unsigned long rsv5[3]; unsigned long unat; unsigned long rsv6[3]; unsigned long fpsr; unsigned long rsv7[3]; unsigned long itc; unsigned long rsv8[3]; unsigned long ign1[16]; unsigned long pfs; /* 64 */ unsigned long lc; unsigned long ec; unsigned long rsv9[45]; unsigned long ign2[16]; };};union vcpu_cr_regs { unsigned long cr[128]; struct { unsigned long dcr; // CR0 unsigned long itm; unsigned long iva; unsigned long rsv1[5]; unsigned long pta; // CR8 unsigned long rsv2[7]; unsigned long ipsr; // CR16 unsigned long isr; unsigned long rsv3; unsigned long iip; unsigned long ifa; unsigned long itir; unsigned long iipa; unsigned long ifs; unsigned long iim; // CR24 unsigned long iha; unsigned long rsv4[38]; unsigned long lid; // CR64 unsigned long ivr; unsigned long tpr; unsigned long eoi; unsigned long irr[4]; unsigned long itv; // CR72 unsigned long pmv; unsigned long cmcv; unsigned long rsv5[5]; unsigned long lrr0; // CR80 unsigned long lrr1; unsigned long rsv6[46]; };};struct vcpu_guest_context_regs { unsigned long r[32]; unsigned long b[8]; unsigned long bank[16]; unsigned long ip; unsigned long psr; unsigned long cfm; unsigned long pr; unsigned int nats; /* NaT bits for r1-r31. */ unsigned int bnats; /* Nat bits for banked registers. */ union vcpu_ar_regs ar; union vcpu_cr_regs cr; struct pt_fpreg f[128]; unsigned long dbr[8]; unsigned long ibr[8]; unsigned long rr[8]; unsigned long pkr[16]; /* FIXME: cpuid,pmd,pmc */ unsigned long xip; unsigned long xpsr; unsigned long xfs; unsigned long xr[4]; struct vcpu_tr_regs tr; /* Physical registers in case of debug event. */ unsigned long excp_iipa; unsigned long excp_ifa; unsigned long excp_isr; unsigned int excp_vector; /* * The rbs is intended to be the image of the stacked registers still * in the cpu (not yet stored in memory). It is laid out as if it * were written in memory at a 512 (64*8) aligned address + offset. * rbs_voff is (offset / 8). rbs_nat contains NaT bits for the * remaining rbs registers. rbs_rnat contains NaT bits for in memory * rbs registers. * Note: loadrs is 2**14 bytes == 2**11 slots. */ unsigned int rbs_voff; unsigned long rbs[2048]; unsigned long rbs_rnat; /* * RSE.N_STACKED_PHYS via PAL_RSE_INFO * Strictly this isn't cpu context, but this value is necessary * for domain save/restore. So is here. */ unsigned long num_phys_stacked;};struct vcpu_guest_context {#define VGCF_EXTRA_REGS (1UL << 1) /* Set extra regs. */#define VGCF_SET_CR_IRR (1UL << 2) /* Set cr_irr[0:3]. */ unsigned long flags; /* VGCF_* flags */ struct vcpu_guest_context_regs regs; unsigned long event_callback_ip; /* xen doesn't share privregs pages with hvm domain so that this member * doesn't make sense for hvm domain. * ~0UL is already used for INVALID_P2M_ENTRY. */#define VGC_PRIVREGS_HVM (~(-2UL)) unsigned long privregs_pfn;};typedef struct vcpu_guest_context vcpu_guest_context_t;DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);/* dom0 vp op */#define __HYPERVISOR_ia64_dom0vp_op __HYPERVISOR_arch_0/* Map io space in machine address to dom0 physical address space. Currently physical assigned address equals to machine address. */#define IA64_DOM0VP_ioremap 0/* Convert a pseudo physical page frame number to the corresponding machine page frame number. If no page is assigned, INVALID_MFN or GPFN_INV_MASK is returned depending on domain's non-vti/vti mode. */#define IA64_DOM0VP_phystomach 1/* Convert a machine page frame number to the corresponding pseudo physical page frame number of the caller domain. */#define IA64_DOM0VP_machtophys 3/* Reserved for future use. */#define IA64_DOM0VP_iounmap 4/* Unmap and free pages contained in the specified pseudo physical region. */#define IA64_DOM0VP_zap_physmap 5/* Assign machine page frame to dom0's pseudo physical address space. */#define IA64_DOM0VP_add_physmap 6/* expose the p2m table into domain */#define IA64_DOM0VP_expose_p2m 7/* xen perfmon */#define IA64_DOM0VP_perfmon 8/* gmfn version of IA64_DOM0VP_add_physmap */#define IA64_DOM0VP_add_physmap_with_gmfn 9/* get fpswa revision */#define IA64_DOM0VP_fpswa_revision 10/* Add an I/O port space range */#define IA64_DOM0VP_add_io_space 11/* expose the foreign domain's p2m table into privileged domain */#define IA64_DOM0VP_expose_foreign_p2m 12#define IA64_DOM0VP_EFP_ALLOC_PTE 0x1 /* allocate p2m table *//* unexpose the foreign domain's p2m table into privileged domain */#define IA64_DOM0VP_unexpose_foreign_p2m 13// flags for page assignement to pseudo physical address space#define _ASSIGN_readonly 0#define ASSIGN_readonly (1UL << _ASSIGN_readonly)#define ASSIGN_writable (0UL << _ASSIGN_readonly) // dummy flag/* Internal only: memory attribute must be WC/UC/UCE. */#define _ASSIGN_nocache 1#define ASSIGN_nocache (1UL << _ASSIGN_nocache)// tlb tracking#define _ASSIGN_tlb_track 2#define ASSIGN_tlb_track (1UL << _ASSIGN_tlb_track)/* Internal only: associated with PGC_allocated bit */#define _ASSIGN_pgc_allocated 3#define ASSIGN_pgc_allocated (1UL << _ASSIGN_pgc_allocated)/* This structure has the same layout of struct ia64_boot_param, defined in <asm/system.h>. It is redefined here to ease use. */struct xen_ia64_boot_param { unsigned long command_line; /* physical address of cmd line args */ unsigned long efi_systab; /* physical address of EFI system table */ unsigned long efi_memmap; /* physical address of EFI memory map */ unsigned long efi_memmap_size; /* size of EFI memory map */ unsigned long efi_memdesc_size; /* size of an EFI memory map descriptor */ unsigned int efi_memdesc_version; /* memory descriptor version */ struct { unsigned short num_cols; /* number of columns on console. */ unsigned short num_rows; /* number of rows on console. */ unsigned short orig_x; /* cursor's x position */ unsigned short orig_y; /* cursor's y position */ } console_info; unsigned long fpswa; /* physical address of the fpswa interface */ unsigned long initrd_start; unsigned long initrd_size; unsigned long domain_start; /* va where the boot time domain begins */ unsigned long domain_size; /* how big is the boot domain */};#endif /* !__ASSEMBLY__ *//* Size of the shared_info area (this is not related to page size). */#define XSI_SHIFT 14#define XSI_SIZE (1 << XSI_SHIFT)/* Log size of mapped_regs area (64 KB - only 4KB is used). */#define XMAPPEDREGS_SHIFT 12#define XMAPPEDREGS_SIZE (1 << XMAPPEDREGS_SHIFT)/* Offset of XASI (Xen arch shared info) wrt XSI_BASE. */#define XMAPPEDREGS_OFS XSI_SIZE/* Hyperprivops. */#define HYPERPRIVOP_START 0x1#define HYPERPRIVOP_RFI (HYPERPRIVOP_START + 0x0)#define HYPERPRIVOP_RSM_DT (HYPERPRIVOP_START + 0x1)#define HYPERPRIVOP_SSM_DT (HYPERPRIVOP_START + 0x2)#define HYPERPRIVOP_COVER (HYPERPRIVOP_START + 0x3)#define HYPERPRIVOP_ITC_D (HYPERPRIVOP_START + 0x4)#define HYPERPRIVOP_ITC_I (HYPERPRIVOP_START + 0x5)#define HYPERPRIVOP_SSM_I (HYPERPRIVOP_START + 0x6)#define HYPERPRIVOP_GET_IVR (HYPERPRIVOP_START + 0x7)#define HYPERPRIVOP_GET_TPR (HYPERPRIVOP_START + 0x8)#define HYPERPRIVOP_SET_TPR (HYPERPRIVOP_START + 0x9)#define HYPERPRIVOP_EOI (HYPERPRIVOP_START + 0xa)#define HYPERPRIVOP_SET_ITM (HYPERPRIVOP_START + 0xb)#define HYPERPRIVOP_THASH (HYPERPRIVOP_START + 0xc)#define HYPERPRIVOP_PTC_GA (HYPERPRIVOP_START + 0xd)#define HYPERPRIVOP_ITR_D (HYPERPRIVOP_START + 0xe)#define HYPERPRIVOP_GET_RR (HYPERPRIVOP_START + 0xf)#define HYPERPRIVOP_SET_RR (HYPERPRIVOP_START + 0x10)#define HYPERPRIVOP_SET_KR (HYPERPRIVOP_START + 0x11)#define HYPERPRIVOP_FC (HYPERPRIVOP_START + 0x12)#define HYPERPRIVOP_GET_CPUID (HYPERPRIVOP_START + 0x13)#define HYPERPRIVOP_GET_PMD (HYPERPRIVOP_START + 0x14)#define HYPERPRIVOP_GET_EFLAG (HYPERPRIVOP_START + 0x15)#define HYPERPRIVOP_SET_EFLAG (HYPERPRIVOP_START + 0x16)#define HYPERPRIVOP_RSM_BE (HYPERPRIVOP_START + 0x17)#define HYPERPRIVOP_GET_PSR (HYPERPRIVOP_START + 0x18)#define HYPERPRIVOP_SET_RR0_TO_RR4 (HYPERPRIVOP_START + 0x19)#define HYPERPRIVOP_MAX (0x1a)/* Fast and light hypercalls. */#define __HYPERVISOR_ia64_fast_eoi __HYPERVISOR_arch_1/* Extra debug features. */#define __HYPERVISOR_ia64_debug_op __HYPERVISOR_arch_2/* Xencomm macros. */#define XENCOMM_INLINE_MASK 0xf800000000000000UL#define XENCOMM_INLINE_FLAG 0x8000000000000000UL#ifndef __ASSEMBLY__/* * Optimization features. * The hypervisor may do some special optimizations for guests. This hypercall * can be used to switch on/of these special optimizations. */#define __HYPERVISOR_opt_feature 0x700UL#define XEN_IA64_OPTF_OFF 0x0#define XEN_IA64_OPTF_ON 0x1/* * If this feature is switched on, the hypervisor inserts the * tlb entries without calling the guests traphandler. * This is useful in guests using region 7 for identity mapping * like the linux kernel does. */#define XEN_IA64_OPTF_IDENT_MAP_REG7 1/* Identity mapping of region 4 addresses in HVM. */#define XEN_IA64_OPTF_IDENT_MAP_REG4 2/* Identity mapping of region 5 addresses in HVM. */#define XEN_IA64_OPTF_IDENT_MAP_REG5 3#define XEN_IA64_OPTF_IDENT_MAP_NOT_SET (0)struct xen_ia64_opt_feature { unsigned long cmd; /* Which feature */ unsigned char on; /* Switch feature on/off */ union { struct { /* The page protection bit mask of the pte. * This will be or'ed with the pte. */ unsigned long pgprot; unsigned long key; /* A protection key for itir. */ }; };};#endif /* __ASSEMBLY__ *//* xen perfmon */#ifdef XEN#ifndef __ASSEMBLY__#ifndef _ASM_IA64_PERFMON_H#include <xen/list.h> // asm/perfmon.h requires struct list_head#include <asm/perfmon.h>// for PFM_xxx and pfarg_features_t, pfarg_context_t, pfarg_reg_t, pfarg_load_t#endif /* _ASM_IA64_PERFMON_H */DEFINE_XEN_GUEST_HANDLE(pfarg_features_t);DEFINE_XEN_GUEST_HANDLE(pfarg_context_t);DEFINE_XEN_GUEST_HANDLE(pfarg_reg_t);DEFINE_XEN_GUEST_HANDLE(pfarg_load_t);#endif /* __ASSEMBLY__ */#endif /* XEN */#endif /* __HYPERVISOR_IF_IA64_H__ *//* * Local variables: * mode: C * c-set-style: "BSD" * c-basic-offset: 4 * tab-width: 4 * indent-tabs-mode: nil * End: */⌨️ 快捷键说明
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