sh7750_regs.h

xen 3.2.2 源码

#define SH7750_RFCR           SH7750_P4_REG32(SH7750_RFCR_REGOFS)
#define SH7750_RFCR_A7        SH7750_A7_REG32(SH7750_RFCR_REGOFS)

#define SH7750_RFCR_KEY       0xA400	/* RFCR write key */

/*
 * Direct Memory Access Controller (DMAC)
 */

/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
#define SH7750_SAR_REGOFS(n)  (0xA00000 + ((n)*16))	/* offset */
#define SH7750_SAR(n)         SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR_A7(n)      SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR0           SH7750_SAR(0)
#define SH7750_SAR1           SH7750_SAR(1)
#define SH7750_SAR2           SH7750_SAR(2)
#define SH7750_SAR3           SH7750_SAR(3)
#define SH7750_SAR0_A7        SH7750_SAR_A7(0)
#define SH7750_SAR1_A7        SH7750_SAR_A7(1)
#define SH7750_SAR2_A7        SH7750_SAR_A7(2)
#define SH7750_SAR3_A7        SH7750_SAR_A7(3)

/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
#define SH7750_DAR_REGOFS(n)  (0xA00004 + ((n)*16))	/* offset */
#define SH7750_DAR(n)         SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR_A7(n)      SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR0           SH7750_DAR(0)
#define SH7750_DAR1           SH7750_DAR(1)
#define SH7750_DAR2           SH7750_DAR(2)
#define SH7750_DAR3           SH7750_DAR(3)
#define SH7750_DAR0_A7        SH7750_DAR_A7(0)
#define SH7750_DAR1_A7        SH7750_DAR_A7(1)
#define SH7750_DAR2_A7        SH7750_DAR_A7(2)
#define SH7750_DAR3_A7        SH7750_DAR_A7(3)

/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
#define SH7750_DMATCR_REGOFS(n)  (0xA00008 + ((n)*16))	/* offset */
#define SH7750_DMATCR(n)      SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR_A7(n)   SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR0_P4     SH7750_DMATCR(0)
#define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
#define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
#define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
#define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
#define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
#define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
#define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)

/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
#define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n)*16))	/* offset */
#define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR0          SH7750_CHCR(0)
#define SH7750_CHCR1          SH7750_CHCR(1)
#define SH7750_CHCR2          SH7750_CHCR(2)
#define SH7750_CHCR3          SH7750_CHCR(3)
#define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
#define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
#define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
#define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)

#define SH7750_CHCR_SSA       0xE0000000	/* Source Address Space Attribute */
#define SH7750_CHCR_SSA_PCMCIA  0x00000000	/* Reserved in PCMCIA access */
#define SH7750_CHCR_SSA_DYNBSZ  0x20000000	/* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_SSA_IO8     0x40000000	/* 8-bit I/O space */
#define SH7750_CHCR_SSA_IO16    0x60000000	/* 16-bit I/O space */
#define SH7750_CHCR_SSA_CMEM8   0x80000000	/* 8-bit common memory space */
#define SH7750_CHCR_SSA_CMEM16  0xA0000000	/* 16-bit common memory space */
#define SH7750_CHCR_SSA_AMEM8   0xC0000000	/* 8-bit attribute memory space */
#define SH7750_CHCR_SSA_AMEM16  0xE0000000	/* 16-bit attribute memory space */

#define SH7750_CHCR_STC       0x10000000	/* Source Address Wait Control Select,
						   specifies CS5 or CS6 space wait
						   control for PCMCIA access */

#define SH7750_CHCR_DSA       0x0E000000	/* Source Address Space Attribute */
#define SH7750_CHCR_DSA_PCMCIA  0x00000000	/* Reserved in PCMCIA access */
#define SH7750_CHCR_DSA_DYNBSZ  0x02000000	/* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_DSA_IO8     0x04000000	/* 8-bit I/O space */
#define SH7750_CHCR_DSA_IO16    0x06000000	/* 16-bit I/O space */
#define SH7750_CHCR_DSA_CMEM8   0x08000000	/* 8-bit common memory space */
#define SH7750_CHCR_DSA_CMEM16  0x0A000000	/* 16-bit common memory space */
#define SH7750_CHCR_DSA_AMEM8   0x0C000000	/* 8-bit attribute memory space */
#define SH7750_CHCR_DSA_AMEM16  0x0E000000	/* 16-bit attribute memory space */

#define SH7750_CHCR_DTC       0x01000000	/* Destination Address Wait Control
						   Select, specifies CS5 or CS6 
						   space wait control for PCMCIA
						   access */

#define SH7750_CHCR_DS        0x00080000	/* DREQ\ Select : */
#define SH7750_CHCR_DS_LOWLVL 0x00000000	/*     Low Level Detection */
#define SH7750_CHCR_DS_FALL   0x00080000	/*     Falling Edge Detection */

#define SH7750_CHCR_RL        0x00040000	/* Request Check Level: */
#define SH7750_CHCR_RL_ACTH   0x00000000	/*     DRAK is an active high out */
#define SH7750_CHCR_RL_ACTL   0x00040000	/*     DRAK is an active low out */

#define SH7750_CHCR_AM        0x00020000	/* Acknowledge Mode: */
#define SH7750_CHCR_AM_RD     0x00000000	/*     DACK is output in read cycle */
#define SH7750_CHCR_AM_WR     0x00020000	/*     DACK is output in write cycle */

#define SH7750_CHCR_AL        0x00010000	/* Acknowledge Level: */
#define SH7750_CHCR_AL_ACTH   0x00000000	/*     DACK is an active high out */
#define SH7750_CHCR_AL_ACTL   0x00010000	/*     DACK is an active low out */

#define SH7750_CHCR_DM        0x0000C000	/* Destination Address Mode: */
#define SH7750_CHCR_DM_FIX    0x00000000	/*     Destination Addr Fixed */
#define SH7750_CHCR_DM_INC    0x00004000	/*     Destination Addr Incremented */
#define SH7750_CHCR_DM_DEC    0x00008000	/*     Destination Addr Decremented */

#define SH7750_CHCR_SM        0x00003000	/* Source Address Mode: */
#define SH7750_CHCR_SM_FIX    0x00000000	/*     Source Addr Fixed */
#define SH7750_CHCR_SM_INC    0x00001000	/*     Source Addr Incremented */
#define SH7750_CHCR_SM_DEC    0x00002000	/*     Source Addr Decremented */

#define SH7750_CHCR_RS        0x00000F00	/* Request Source Select: */
#define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000	/* External Request, Dual Address
						   Mode (External Addr Space->
						   External Addr Space) */
#define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200	/* External Request, Single
						   Address Mode (External Addr
						   Space -> External Device) */
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300	/* External Request, Single
						   Address Mode, (External 
						   Device -> External Addr 
						   Space) */
#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400	/* Auto-Request (External Addr
						   Space -> External Addr Space) */

#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500	/* Auto-Request (External Addr
						   Space -> On-chip Peripheral
						   Module) */
#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600	/* Auto-Request (On-chip 
						   Peripheral Module ->
						   External Addr Space */
#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800	/* SCI Transmit-Data-Empty intr
						   transfer request (external
						   address space -> SCTDR1) */
#define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900	/* SCI Receive-Data-Full intr
						   transfer request (SCRDR1 ->
						   External Addr Space) */
#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00	/* SCIF Transmit-Data-Empty intr
						   transfer request (external
						   address space -> SCFTDR1) */
#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00	/* SCIF Receive-Data-Full intr
						   transfer request (SCFRDR2 ->
						   External Addr Space) */
#define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00	/* TMU Channel 2 (input capture
						   interrupt), (external address
						   space -> external address
						   space) */
#define SH7750_CHCR_RS_TMU2_EA_TO_OCP   0xD00	/* TMU Channel 2 (input capture
						   interrupt), (external address
						   space -> on-chip peripheral
						   module) */
#define SH7750_CHCR_RS_TMU2_OCP_TO_EA   0xE00	/* TMU Channel 2 (input capture
						   interrupt), (on-chip
						   peripheral module -> external
						   address space) */

#define SH7750_CHCR_TM        0x00000080	/* Transmit mode: */
#define SH7750_CHCR_TM_CSTEAL 0x00000000	/*     Cycle Steal Mode */
#define SH7750_CHCR_TM_BURST  0x00000080	/*     Burst Mode */

#define SH7750_CHCR_TS        0x00000070	/* Transmit Size: */
#define SH7750_CHCR_TS_QUAD   0x00000000	/*     Quadword Size (64 bits) */
#define SH7750_CHCR_TS_BYTE   0x00000010	/*     Byte Size (8 bit) */
#define SH7750_CHCR_TS_WORD   0x00000020	/*     Word Size (16 bit) */
#define SH7750_CHCR_TS_LONG   0x00000030	/*     Longword Size (32 bit) */
#define SH7750_CHCR_TS_BLOCK  0x00000040	/*     32-byte block transfer */

#define SH7750_CHCR_IE        0x00000004	/* Interrupt Enable */
#define SH7750_CHCR_TE        0x00000002	/* Transfer End */
#define SH7750_CHCR_DE        0x00000001	/* DMAC Enable */

/* DMA Operation Register - DMAOR */
#define SH7750_DMAOR_REGOFS   0xA00040	/* offset */
#define SH7750_DMAOR          SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
#define SH7750_DMAOR_A7       SH7750_A7_REG32(SH7750_DMAOR_REGOFS)

#define SH7750_DMAOR_DDT      0x00008000	/* On-Demand Data Transfer Mode */

#define SH7750_DMAOR_PR       0x00000300	/* Priority Mode: */
#define SH7750_DMAOR_PR_0123  0x00000000	/*     CH0 > CH1 > CH2 > CH3 */
#define SH7750_DMAOR_PR_0231  0x00000100	/*     CH0 > CH2 > CH3 > CH1 */
#define SH7750_DMAOR_PR_2013  0x00000200	/*     CH2 > CH0 > CH1 > CH3 */
#define SH7750_DMAOR_PR_RR    0x00000300	/*     Round-robin mode */

#define SH7750_DMAOR_COD      0x00000010	/* Check Overrun for DREQ\ */
#define SH7750_DMAOR_AE       0x00000004	/* Address Error flag */
#define SH7750_DMAOR_NMIF     0x00000002	/* NMI Flag */
#define SH7750_DMAOR_DME      0x00000001	/* DMAC Master Enable */

/*
 * Serial Communication Interface - SCI
 * Serial Communication Interface with FIFO - SCIF
 */
/* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */
#define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014)	/* offset */
#define SH7750_SCRDR(n)       SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n))
#define SH7750_SCRDR1         SH7750_SCRDR(1)
#define SH7750_SCRDR2         SH7750_SCRDR(2)
#define SH7750_SCRDR_A7(n)    SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n))
#define SH7750_SCRDR1_A7      SH7750_SCRDR_A7(1)
#define SH7750_SCRDR2_A7      SH7750_SCRDR_A7(2)

/* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */
#define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C)	/* offset */
#define SH7750_SCTDR(n)       SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n))
#define SH7750_SCTDR1         SH7750_SCTDR(1)
#define SH7750_SCTDR2         SH7750_SCTDR(2)
#define SH7750_SCTDR_A7(n)    SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n))
#define SH7750_SCTDR1_A7      SH7750_SCTDR_A7(1)
#define SH7750_SCTDR2_A7      SH7750_SCTDR_A7(2)

/* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */
#define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000)	/* offset */
#define SH7750_SCSMR(n)       SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n))
#define SH7750_SCSMR1         SH7750_SCSMR(1)
#define SH7750_SCSMR2         SH7750_SCSMR(2)
#define SH7750_SCSMR_A7(n)    SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n))
#define SH7750_SCSMR1_A7      SH7750_SCSMR_A7(1)
#define SH7750_SCSMR2_A7      SH7750_SCSMR_A7(2)

#define SH7750_SCSMR1_CA       0x80	/* Communication Mode (C/A\): */
#define SH7750_SCSMR1_CA_ASYNC 0x00	/*     Asynchronous Mode */
#define SH7750_SCSMR1_CA_SYNC  0x80	/*     Synchronous Mode */
#define SH7750_SCSMR_CHR       0x40	/* Character Length: */
#define SH7750_SCSMR_CHR_8     0x00	/*     8-bit data */
#define SH7750_SCSMR_CHR_7     0x40	/*     7-bit data */
#define SH7750_SCSMR_PE        0x20	/* Parity Enable */
#define SH7750_SCSMR_PM        0x10	/* Parity Mode: */
#define SH7750_SCSMR_PM_EVEN   0x00	/*     Even Parity */
#define SH7750_SCSMR_PM_ODD    0x10	/*     Odd Parity */
#define SH7750_SCSMR_STOP      0x08	/* Stop Bit Length: */
#define SH7750_SCSMR_STOP_1    0x00	/*     1 stop bit */
#define SH7750_SCSMR_STOP_2    0x08	/*     2 stop bit */
#define SH7750_SCSMR1_MP       0x04	/* Multiprocessor Mode */
#define SH7750_SCSMR_CKS       0x03	/* Clock Select */
#define SH7750_SCSMR_CKS_S     0
#define SH7750_SCSMR_CKS_DIV1  0x00	/*     Periph clock */
#define SH7750_SCSMR_CKS_DIV4  0x01	/*     Periph clock / 4 */
#define SH7750_SCSMR_CKS_DIV16 0x02	/*     Periph clock / 16 */
#define SH7750_SCSMR_CKS_DIV64 0x03	/*     Periph clock / 64 */

/* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */
#define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008)	/* offset */
#define SH7750_SCSCR(n)       SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n))
#define SH7750_SCSCR1         SH7750_SCSCR(1)
#define SH7750_SCSCR2         SH7750_SCSCR(2)
#define SH7750_SCSCR_A7(n)    SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n))
#define SH7750_SCSCR1_A7      SH7750_SCSCR_A7(1)
#define SH7750_SCSCR2_A7      SH7750_SCSCR_A7(2)

#define SH7750_SCSCR_TIE      0x80	/* Transmit Interrupt Enable */
#define SH7750_SCSCR_RIE      0x40	/* Receive Interrupt Enable */
#define SH7750_SCSCR_TE       0x20	/* Transmit Enable */
#define SH7750_SCSCR_RE       0x10	/* Receive Enable */
#define SH7750_SCSCR1_MPIE    0x08	/* Multiprocessor Interrupt Enable */
#define SH7750_SCSCR2_REIE    0x08	/* Receive Error Interrupt Enable */
#define SH7750_SCSCR1_TEIE    0x04	/* Transmit End Interrupt Enable */
#define SH7750_SCSCR1_CKE     0x03	/* Clock Enable: */
#define SH7750_SCSCR_CKE_INTCLK            0x00	/