📄 bsp.h
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/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
*
* (c) Copyright 2004, Micrium, Weston, FL
* All Rights Reserved
*
*
* BOARD SUPPORT PACKAGE (BSP)
* Freescale MC9S12
*
* File : BSP.H
* By : Eric Shufro
*********************************************************************************************************
*/
#ifndef BSP_H
#define BSP_H
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*********************************************************************************************************
*/
static void BSP_SetECT_Prescaler(INT8U prescaler);
void BSP_Init (void);
void LED_Off(INT8U led);
void LED_On(INT8U led);
void LED_Toggle(INT8U led);
void BSP_DlyMS(INT8U ms);
INT32U BSP_CPU_ClkFreq(void);
/*
*********************************************************************************************************
* PROCESSOR SPECIFICS
*********************************************************************************************************
*/
/*-----------------------------------------------------*/
/* OS TICKER SETUP */
/*-----------------------------------------------------*/
#define OS_TICK_OC 7 /* Output comp. channel # used to generate a tick Int (5-7)*/
/* The NE64 has 4-7, but 4 is reserved for ECT based PWM */
/*-----------------------------------------------------*/
/* SYSTEM CLOCK SETUP */
/*-----------------------------------------------------*/
#define OSCFREQ 25000000L /* Define the system crystal (oscillator) speed as 25MHZ */
/* Since this is the xtal on the Demo MC9S12NE64 EVB */
#define PLL_EN 0 /* Select whether the PLL should be enabled. 0=No, 1=Yes */
#define PLL_CLK_MUL 0 /* For MC9S12NE64, this value MUST never be > 0 when using */
/* a crystal >= 25MHZ. 50MHZ is CPU's MAXIMUM SPD and the */
/* PLL multiplies (OSCFREQ * 2) when switched on. */
#define PLL_CLK_DIV 0 /* Set the PLL Divider. Can be 0-15. Setting 0 has value=1 */
#if PLL_EN == 0
#define SYSCLK OSCFREQ /* If PLL disabled, then SYSCLOCK = OSCCLK */
#define BUS_CLK_FREQ (SYSCLK / 2) /* BUSCLK = SYSCLK / 2 */
#else
#define PLLCLK ((OSCFREQ * 2) * (PLL_CLK_MUL + 1) / (PLL_CLK_DIV + 1))
#define BUS_CLK_FREQ (PLLCLK / 2) /* BUSCLK = PLLCLK / 2 */
#endif
/*
*********************************************************************************************************
* ERROR CHECKING
*********************************************************************************************************
*/
#ifndef PLL_EN
#error "PLL_EN must be defined in bsp.h. 0 = PLL Disabled, 1 = PLL Enabled"
#endif
#if PLL_EN == 1
#ifndef PLL_CLK_MUL
#error "PLL_CLK_MUL must be defined in bsp.h. if PLL_EN is 0 for 25mhz crystal"
#endif
#ifndef PLL_CLK_DIV
#error "PLL_CLK_DIV must be defined in bsp.h. if PLL_EN is 0 for 25mhz crystal"
#endif
#if PLL_CLK_MUL > 63
#error "PLL_CLK_MUL must must have a value between 0 and 63"
#endif
#if PLL_CLK_DIV > 15
#error "PLL_CLK_DIV must have a value between 0 and 15"
#endif
#endif
#ifndef OSCFREQ
#error "OSCFREQ must be defined in bsp.h"
#endif
#ifndef BUS_CLK_FREQ
#error "BUS_CLK_FREQ must be defined in bsp.h."
#endif
#if BUS_CLK_FREQ > 25000000L
#error "BUS_CLK_FREQ configuration error in bsp.h (WARNING: BUS_CLK_FREQ > 24 MHZ!)"
#endif
#if (OS_TICK_OC < 5) && (OS_TICK_OC > 7)
#error "OS_TICK_OC is illegally defined in bsp.h. Expected valued between 4-7."
#endif
#endif
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