📄 bulkloop.lst
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C51 COMPILER V7.06 BULKLOOP 10/15/2007 20:16:02 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE BULKLOOP
OBJECT MODULE PLACED IN bulkloop.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE bulkloop.c DEBUG OBJECTEXTEND
stmt level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: FX2_to_extsyncFIFO.c
4 // Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
5 // interface using CY4265-15AC
6 //
7 // Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
8 //-----------------------------------------------------------------------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
12 #include "application.h"
13 #include "isr.h" // Ref. Manual for usage details.
14
15 #define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
16 #define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
17
18 #define GPIFTRIGRD 4
19
20 #define GPIF_EP2 0
21 #define GPIF_EP4 1
22 #define GPIF_EP6 2
23 #define GPIF_EP8 3
24
25 extern BOOL GotSUD; // Received setup data flag
26 extern BOOL Sleep;
27 extern BOOL Rwuen;
28 extern BOOL Selfpwr;
29
30 BYTE temp1,temp2,temp3;
31 BYTE Configuration; // Current configuration
32 BYTE AlternateSetting; // Alternate settings
33 BOOL in_enable = FALSE; // flag to enable IN transfers
34 BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
35 extern const char xdata FlowStates[36];
36
37 //-----------------------------------------------------------------------------
38 // Task Dispatcher hooks
39 // The following hooks are called by the task dispatcher.
40 //-----------------------------------------------------------------------------
41
42 void GpifInit ();
43
44 void TD_Init(void) // Called once at startup
45 {
46 1 // set the CPU clock to 12MHz
47 1 //CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
48 1 CPUCS = 0x02;
49 1 SYNCDELAY;
50 1
51 1 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
52 1 SYNCDELAY;
53 1 EP4CFG = 0x00; // EP4 not valid
54 1 SYNCDELAY;
55 1 EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
C51 COMPILER V7.06 BULKLOOP 10/15/2007 20:16:02 PAGE 2
56 1 SYNCDELAY;
57 1 EP8CFG = 0x00; // EP8 not valid
58 1 SYNCDELAY;
59 1
60 1
61 1 FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
62 1 SYNCDELAY;
63 1 FIFORESET = 0x02; // reset EP2 FIFO
64 1 SYNCDELAY;
65 1 FIFORESET = 0x06; // reset EP6 FIFO
66 1 SYNCDELAY;
67 1 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
68 1 SYNCDELAY;
69 1
70 1 EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
71 1 SYNCDELAY;
72 1 EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
73 1 SYNCDELAY;
74 1 EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
75 1 SYNCDELAY;
76 1 OEA = 0xFF;
77 1 DAC_5618(0x02,0x60,0x02);
78 1 // Timer0_Init();
79 1 GpifInit();
80 1 Peripheral_SingleWordWrite( 0x0000 );// 控制max275的采集通道
81 1 // EZUSB_Delay(1);
82 1
83 1 SYNCDELAY;
84 1 EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
85 1 SYNCDELAY;
86 1 EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
87 1 SYNCDELAY;
88 1
89 1
90 1 }
91
92 void TD_Poll(void)
93 {
94 1 PA0 =0;
95 1 if ( EP68FIFOFLGS & 0x01 ) //full
96 1 PA0 =1;
97 1 if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
98 1 {
99 2 Peripheral_SingleWordWrite( 0x0000 );// 控制max275的采集通道
100 2 //EZUSB_Delay(1);
101 2 _nop_();
102 2 _nop_();
103 2 _nop_();
104 2 _nop_();
105 2 if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
106 2 {
107 3 Peripheral_SetGPIFTC( 1);//设定读写次数
108 3 _nop_();
109 3 _nop_();
110 3 _nop_();
111 3 _nop_();
112 3 Peripheral_FIFORead( GPIF_EP6 ) ;
113 3 _nop_();
114 3 _nop_();
115 3 _nop_();
116 3 _nop_();
117 3 }
C51 COMPILER V7.06 BULKLOOP 10/15/2007 20:16:02 PAGE 3
118 2 }
119 1 }
120
121 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
122 {
123 1 return(TRUE);
124 1 }
125
126 BOOL TD_Resume(void) // Called after the device resumes
127 {
128 1 return(TRUE);
129 1 }
130
131 //-----------------------------------------------------------------------------
132 // Device Request hooks
133 // The following hooks are called by the end point 0 device request parser.
134 //-----------------------------------------------------------------------------
135
136 BOOL DR_GetDescriptor(void)
137 {
138 1 return(TRUE);
139 1 }
140
141 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
142 {
143 1 if( EZUSB_HIGHSPEED( ) )
144 1 { // FX2 enumerated at high speed
145 2 SYNCDELAY; //
146 2 EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
147 2 SYNCDELAY; //
148 2 EP6AUTOINLENL = 0x00;
149 2 SYNCDELAY;
150 2 enum_high_speed = TRUE;
151 2 }
152 1 else
153 1 { // FX2 enumerated at full speed
154 2 SYNCDELAY;
155 2 EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
156 2 SYNCDELAY;
157 2 EP6AUTOINLENL = 0x40;
158 2 SYNCDELAY;
159 2 enum_high_speed = FALSE;
160 2 }
161 1
162 1 Configuration = SETUPDAT[2];
163 1 return(TRUE); // Handled by user code
164 1 }
165
166 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
167 {
168 1 EP0BUF[0] = Configuration;
169 1 EP0BCH = 0;
170 1 EP0BCL = 1;
171 1 return(TRUE); // Handled by user code
172 1 }
173
174 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
175 {
176 1 AlternateSetting = SETUPDAT[2];
177 1 return(TRUE); // Handled by user code
178 1 }
179
C51 COMPILER V7.06 BULKLOOP 10/15/2007 20:16:02 PAGE 4
180 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
181 {
182 1 EP0BUF[0] = AlternateSetting;
183 1 EP0BCH = 0;
184 1 EP0BCL = 1;
185 1 return(TRUE); // Handled by user code
186 1 }
187
188 BOOL DR_GetStatus(void)
189 {
190 1 return(TRUE);
191 1 }
192
193 BOOL DR_ClearFeature(void)
194 {
195 1 return(TRUE);
196 1 }
197
198 BOOL DR_SetFeature(void)
199 {
200 1 return(TRUE);
201 1 }
202
203 #define VX_B2 0xB2 // reset the external FIFO
204 #define VX_B3 0xB3 // enable IN transfers
205 #define VX_B4 0xB4 // disable IN transfers
206 #define VX_B5 0xB5 // read GPIFREADYSTAT register
207 #define VX_B6 0xB6 // read GPIFTRIG register
208
209 BOOL DR_VendorCmnd(void)
210 {
211 1 switch (SETUPDAT[1])
212 1 {
213 2 case VX_B2:
214 2 {
215 3
216 3 *EP0BUF = VX_B2;
217 3 EP0BCH = 0;
218 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
219 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
220 3 break;
221 3 }
222 2 case VX_B3: // enable IN transfers
223 2 {
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