xor_tri.v

with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,e

module xor_tri_state(x0,x1,y);
input x0,x1;
output y;
tri y;

notif1 n1(y,x0,x1);
bufif0 b1(y,x0,x1);

endmodule

module test;
reg x0,x1;
tri y;

xor_tri_state xo(x0,x1,y);

initial
	begin
		x0=1; x1=0;
		#1 x0=0;x1=0;
		#1 x0=0;x1=1;
		#1 x0=1;x1=1;
	end
initial 
begin
$monitor("x0=%b x1=%b y=%b",x0,x1,y);
end
endmodule