xor.vl

with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,e

          
module not1(x,a);
input a;
output x;
supply1 pwr;
supply0 grd;
pmos p(x,pwr,a);
nmos n(x,grd,a);
endmodule




module xor1 (a, b, w);

          input a, b;

          output w;

          supply1 vdd;

          supply0 gnd;

          wire w1,w2,w3,w4,an,bn;
           not1 n0(an,a); 
          
           not1 n1(bn,b);

          
          nmos(w, w3, a);

          nmos(w, w4, an);

          nmos(w3, gnd, b);

          nmos(w4, gnd, bn);

          pmos(w1, vdd, a);

          pmos(w2, vdd, an);

          pmos(w, w1, bn);

          pmos(w, w2, b);

endmodule





   module testxor();    
      reg A, B;    
        wire out;       
    xor1 n1(A, B, out);
              initial begin   
            
    A=4'b0 ;	B=4'b0 ; 
	#1000	A=4'b0 ;	B=4'b1 ; 
	#1000	A=4'b1 ;	B=4'b0 ; 
	#1000	A=4'b1 ;	B=4'b1 ; 	
			
end
initial begin 


$monitor("A=%b B=%b  out=%b ",A,B,out);  
        
              
 end       
endmodule