evm.v

with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,e

`timescale 1ns / 1ps

module vote(clk,led,butt);

    input clk;
	 output [15:0] led;
	 input [0:6] butt;
	 
	 reg [15:0] led;
    reg [7:0] votes;
    reg [7:0] count_a,count_b,count_c,count_d;
    reg temp;
	 
initial begin
count_a=0; count_b=0;count_c=0;count_d=0;
temp=0;led=0;
end

always@(posedge clk)
begin

if(butt[6])
	begin
   count_a=0;count_b=0;count_c=0; count_d=0;
   temp=0;
	led=0;
	led[7]=1;
end
	
else if(butt[5])
	begin
	led[0]=0;
	temp=0;
	led[5]=1;
	if(count_a>count_b & count_a>count_c & count_a>count_d)
		begin
		led[1]=1;
		end
	
	 else if(count_b>count_a & count_b>count_c & count_b>count_d)
		begin
		led[2]=1;
		end
	

	else if(count_c>count_a & count_c>count_b & count_c>count_d)
		begin
		led[3]=1;
		end
	
	else if(count_d>count_a & count_d>count_b & count_d>count_c)
		begin
		led[4]=1;
		end
	else
	   led[6]=1;
		
		if(butt[0])
		begin 
		votes=count_a;
		end	
		
		else if(butt[1])
		begin 
		votes=count_b;
		end	
		
		else if(butt[2])
		begin 
		votes=count_c;
		end	
		
		else if(butt[3])
		begin 
		votes=count_d;
		end	
		
		else
		  votes=0;
		  
	   led[15:8]=votes;
end

else if(butt[4])
      begin
      temp=1;
		led[0]=1;
end

else if(~butt[5]) 
	    begin
		 led[15:5]=0;
		 votes=0;
end

if( ~ butt[6])
   led[7]=0;

if(temp)
	begin
		
		if(butt[0] | butt[1] | butt[2] | butt[3])
		begin
		temp=0;
		led[0]=0;
		end
		
		if(butt[0])
		begin 
		count_a=count_a+1;
		led[1]=1;
		end	
		
		else if(butt[1])
		begin 
		count_b=count_b+1;
		led[2]=1;
		end	
		
		else if(butt[2])
		begin 
		count_c=count_c+1;
		led[3]=1;
		end	
		
		else if(butt[3])
		begin 
		 count_d=count_d+1;
		 led[4]=1;
		end
end

else if(~butt[0] & ~butt[1] & ~butt[2] & ~butt[3] & ~butt[5])
     led[4:1]=0;
end

endmodule