jkff.vl

with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,e

`define TICK #2
module jkflop(j,k,clk,rst,q);
input j,k,clk,rst;
output q;
reg q;
always @(posedge clk)begin
if(j==1 & k==1 & rst==0)begin
q <=`TICK ~q; //Toggles
end
else if(j==1 & k==0 & rst==0)begin
q <= `TICK 1; //Set
end
else if(j==0 & k==1)begin
q <= `TICK 0; //Cleared
end
end
always @(posedge rst)begin
q <= 0; //The reset normally has negligible delay and hence ignored.
end
endmodule

module main;
reg j,k,clk,rst;
wire q;
jkflop jk(j,k,clk,rst,q);
//Module to generate clock with period 10 time units
initial begin
forever begin
clk=0;
#5
clk=1;
#5
clk=0;
end
end
initial begin
j=0; k=0; rst=1;
#4
j=1; k=1; rst=0;
#40
rst=1;
#10
j=0; k=1;
#10
rst=0;
#10
j=1; k=0;
end
endmodule