mod16c.vl

with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,e

module mod16c(control,load,clk,out);
	input control,load,clk;
	output [3:0]out;
    reg [3:0]out;
initial out=0000;
	always @(negedge clk or posedge clk)
	begin
		if(load)
			out <= 4'b0000;
		else if(control)
		begin
			if(out<16)
				out <= out+1;
			else
				out <= 4'b0000;
		end
		else
			out <= out;
	end
endmodule


module Test();
	reg control,load,clk;
	wire [3:0]out;
	mod16c m1(control,load,clk,out);
always
	#1 clk=!clk;
initial
	begin
		clk=0;control=0;load=0;
	
	#1	control=1;
	#18	$finish;
	end
initial
		$monitor("clk::%b \t control::%b \t load::%b \tout::%0d",clk,control,load,out);
endmodule