dspdef.hec

这是用Labwindows开发的一个RF test程序。 用于日本机种的组装后ANT 测试。

/* a speech frame corresponds to 20 ms          */
/* 500 frames corresponds to 10 seconds         */
#define DSP_MAX_FRAME_COUNTER                   500


#endif /* SPRIDGE_FTR  */

#if defined(DSP_EC_AEC_FTR)
/*======================================================================*/
/* Constants for EV_AUDIO_INIT order length used for AEC Audio Feature  */
/*======================================================================*/
#define DSP_NB_AUDIO_FEATURE_AEC_OFF_PARAM       2
#define DSP_NB_AUDIO_FEATURE_AEC_ON_PARAM        18
#endif /* DSP_EC_AEC_FTR */

/*======================================================================*/
/* converted values for the DTMF generation                             */
/*======================================================================*/
#define DSP_TG_COS_0            32666
#define DSP_TG_SIN_0                0
#define DSP_TG_COS_100          32666
#define DSP_TG_SIN_100           2571
#define DSP_TG_COS_300          31862
#define DSP_TG_SIN_300           7649
#define DSP_TG_COS_425		30959
#define DSP_TG_SIN_425		10736
#define DSP_TG_COS_950		24062
#define DSP_TG_SIN_950		22243
#define DSP_TG_COS_1400		14876
#define DSP_TG_SIN_1400		29197
#define DSP_TG_COS_1800		 5126
#define DSP_TG_SIN_1800		32365
#define DSP_TG_COS_2200         -5126   
#define DSP_TG_SIN_2200         32365     
#define DSP_TG_COS_2600        -14876
#define DSP_TG_SIN_2600         29197
#define DSP_TG_COS_3000        -23170
#define DSP_TG_SIN_3000         23170
#define DSP_TG_COS_3400        -29197
#define DSP_TG_SIN_3400         14876
#define DSP_TG_COS_4000        -32768
#define DSP_TG_SIN_4000             0

/*======================================================================*/
/* definitions for Bad Frame Cancelling                                 */ 
/*======================================================================*/
#if defined(DSP_ADV_MUTE)
#define DSP_BC_ON	    1	/* 1 mean BC activation      */
#define DSP_BC_OFF	    0	/* 0 mean BC deactivation    */

#if defined(ADV_MUTE_FTR_TEST_DURING_HANDOVER_DBG)
#define DSP_BC_HANDO_TIMER 1000  
#else
#define DSP_BC_HANDO_TIMER 40  /* 10 blocks, 10*4 trames    */   
                               /* other values = activation */
#endif /*ADV_MUTE_FTR_TEST_DURING_HANDOVER_DBG*/

#endif /* DSP_ADV_MUTE */

/************************************************************************/
/*  Used with TRACE Tools for DPWS swicth : Frequency, Voltage, AVDDSS  */
/************************************************************************/
/* Frequency Switch */
#define DSP_TRACE_FREQUENCY_52MHZ   52
#define DSP_TRACE_FREQUENCY_26MHZ   26
#define DSP_TRACE_FREQUENCY_13MHZ   13

/* Voltage Switch */
#define DSP_TRACE_VOLTAGE_2V35     235
#define DSP_TRACE_VOLTAGE_1V65     165
#define DSP_TRACE_VOLTAGE_1V35     135

/* AVDDSS Switch */
#define DSP_TRACE_AVDDSS_ON          1
#define DSP_TRACE_AVDDSS_OFF         0

/*+ LMSdv88514 - Begin - 15/05/03 - C. DOUMENC */
#if defined(PR_DDTS_88514_QBC_START_FI_TMP)
#define DSP_HWL_QBC_START_FI_DBG		   0xBB00 
#else
#define DSP_HWL_QBC_START_FI_DBG		   0xAA00 
#endif
/*- LMSdv88514 - End */
#define DSP_HWL_QBC_STOP_FI_DBG 	           0xAB00 
#define DSP_HWL_QBC_START_HANDLE_RESULT_DBG 	   0xAC00 
#define DSP_HWL_QBC_STOP_HANDLE_RESULT_DBG 	   0xAD00 

#define DSP_HWL_QBC_START_SIM_DBG 	   0xAE00 
#define DSP_HWL_QBC_STOP_SIM_DBG 	   0xAF00 
#define DSP_HWL_QBC_START_RXUART0_DBG 	   0xB100 
#define DSP_HWL_QBC_STOP_RXUART0_DBG 	   0xB200 
#define DSP_HWL_QBC_START_TXUART0_DBG 	   0xB300 
#define DSP_HWL_QBC_STOP_TXUART0_DBG 	   0xB400 
#define DSP_HWL_QBC_START_RXUART1_DBG 	   0xB500 
#define DSP_HWL_QBC_STOP_RXUART1_DBG 	   0xB600 
#define DSP_HWL_QBC_START_TXUART1_DBG 	   0xB700 
#define DSP_HWL_QBC_STOP_TXUART1_DBG 	   0xB800 

#define DSP_IQ_READWRITE_POINTER_DBG 	   0xB900

/*======================================================================*/
/* Constant for HWL/TAT interface                                       */ 
/*======================================================================*/

#if defined (RF_UAA3537_HDW)
#define DSP_RF_COMPONENT 1
#define DSP_BBI_COMPONENT 2
#endif /*if defined (RF_UAA3537_HDW)*/

#define DSP_TAT_NO_RESOURCE 0
#define DSP_TAT_DCOFFSET_RESOURCE 1
#define DSP_TAT_MONITORING_RESOURCE 2
#define DSP_TAT_MONITORINGFIXEDAGC_RESOURCE 3

#if defined(ACCESS_RIGHTS_TATRF)||defined(ACCESS_RIGHTS_TATDSP) ||\
    defined(ACCESS_RIGHTS_DSP)||defined(ACCESS_RIGHTS_DVRF)||\
    defined(ACCESS_RIGHTS_IHMRF)

#define DSP_TAT_RX_GSM_RESOURCE 4
#define DSP_TAT_RX_GPRS_RESOURCE 5

#endif

#define DSP_TAT_TX_RESOURCE 6
#define DSP_TAT_TXFILLBUFFER_RESOURCE 7
#define DSP_TAT_TXRACH_RESOURCE 8
#define DSP_TAT_INTERFERENCE_RESOURCE 9
#define DSP_TAT_RX_RESOURCE 10

#define DSP_TAT_TX_TRS_MODE_SIN00 0
#define DSP_TAT_TX_TRS_MODE_SIN01 1
#define DSP_TAT_TX_TRS_MODE_TCH_FIXED 2
#define DSP_TAT_TX_TRS_MODE_TCH_RANDOM 3

#define DSP_TAT_TX_NO_TRS_MODE_SIN00 0
#define DSP_TAT_TX_NO_TRS_MODE_SIN01 1


#define DSP_TAT_MAX_FRAME_RESOURCE 8
#define DSP_NB_TIMESLOT_IN_FRAME 8
#define DSP_TAT_MAX_FOLLOWING_TX_RESOURCE 4
#define DSP_GPRS_MODE TRUE
#define DSP_GSM_MODE  FALSE
#define DSP_TAT_BURST2  2
#define DSP_TAT_BSIC 0
#define DSP_NOT_A_RACH_WHILE_TCH 0
#define DSP_TAT_RACH_NOT_EXTENTED 0
#define DSP_TAT_RACH_DATA 0
#define DSP_TAT_START_PDTCH_Ttb 1
#define DSP_TAT_TSC_0 0

#if defined(AMR_FTR)
/************************************************************************/
/*  Used by L1 for AMR                                                  */
/************************************************************************/

/* ConfigType */
#define DSP_TCH_STANDARD_INIT   0
#define DSP_TCH_KEEP_OLD_CONFIG 1

/* vp_save_config */
#define DSP_TCH_SAVE_CONFIG    0
#define DSP_TCH_NO_SAVE_CONFIG 1

/* RX_Flag */
#define DSP_VALID_RX    1
#define DSP_NOTVALID_RX 0

/* FrameType */
/* PR79762 correction: bad declaration of the following constant have been corrected */
#define DSP_DL_SPEECH_GOOD      0x00
#define DSP_DL_SPEECH_DEGRADED  0x01
#define DSP_DL_ONSET            0x02
#define DSP_DL_SPEECH_BAD       0x03
#define DSP_DL_SID_FIRST        0x04
#define DSP_DL_SID_UPDATE       0x05
#define DSP_DL_SID_BAD          0x06
#define DSP_DL_NO_DATA          0x07
/* End PR79762 */

#define DSP_UL_ENC_OUT_SPEECH   0x00
#define DSP_UL_ENC_SID_FIRST    0x01
#define DSP_UL_ENC_SID_UPDATE   0x02
#define DSP_UL_ENC_NO_DATA      0x03
#define DSP_UL_ENC_FACCH_FRM    0x04
#define DSP_UL_ENC_RATSCCH_FRM  0x05

/* AMR codec */
#define DSP_AMR_CODEC_475       0x00
#define DSP_AMR_CODEC_51        0x01
#define DSP_AMR_CODEC_59        0x02
#define DSP_AMR_CODEC_67        0x03
#define DSP_AMR_CODEC_74        0x04
#define DSP_AMR_CODEC_795       0x05
#define DSP_AMR_CODEC_102       0x06
#define DSP_AMR_CODEC_122       0x07

#if defined(PLAY_RECORD_AMR_FTR)
#define DSP_AMR_SID             0x08
#define DSP_GSM-EFR_SID         0x09
#define DSP_TDMA-EFR_SID        0x0A
#define DSP_PDC-EFR_SID         0x0B
#define DSP_AMR_NODATA          0x0F
#endif

/* AMR mode */
#define DSP_AMR_MODE_1          0x00
#define DSP_AMR_MODE_2          0x01
#define DSP_AMR_MODE_3          0x02
#define DSP_AMR_MODE_4          0x03

/* RATSCCH Req */
#define DSP_REQ_NO_DATA          0x00
#define DSP_CMI_PHASE_REQ        0x01
#define DSP_AMR_CONFIG_REQ_MSG_1 0x02
#define DSP_AMR_CONFIG_REQ_MSG_2 0x03
#define DSP_TRESH_REQ_MSG        0x04

/* RATSCCH Ack */
#define DSP_ACK_NO_DATA          0x00
#define DSP_ACK_OK_MSG           0x01
#define DSP_ACK_ERR_MSG          0x02
#define DSP_ACK_UNKNOWN_MSG      0x03

#endif /* AMR_FTR */

/************************************************************************/
/*  Used for VCO IF switch OFF of the 5178                              */
/************************************************************************/
#if (!defined(RADIO_3536_HDW) && !defined(RF_UAA3537_HDW))
#define DSP_TXIF_OFF_LEN             2
#else /*if (!defined(RADIO_3536_HDW) && !defined(RF_UAA3537_HDW))*/
#define DSP_TXIF_OFF_LEN             0
#endif /* if (!defined(RADIO_3536_HDW) && !defined(RF_UAA3537_HDW)) */

#if defined(EOTD_FTR)
/*======================================================================*/
/* Constant for EOTD feature                                            */ 
/*======================================================================*/
#define DSP_NB_CORRELATION         MP_EOTD_DSP_LENGTH
#endif

/************************************************************************/
/*         Radio constant defined by HWL for L1 algorithm		*/
/************************************************************************/
#define DSP_AGC_INIT_VALUE		-200 /* -100dBm */
#define DSP_AGC_STEP_INITIAL_SYNCHRO	48 /* 24dB */
#define DSP_AGC_STEP_POWER_ADJUST	8 /* 4dB */
#define DSP_AGC_LOW_LIMIT_CRITERIA	60 /* 30dB */
#define DSP_AGC_HIGH_LIMIT_CRITERIA	20 /*10dB */

/************************************************************************/
/*         Patch NJO on synthe continuous				*/
/************************************************************************/
#if defined(DSP_MT_CV1_HDW)
#define DSP_MP_NEXT_MASK	0xA1A7
#endif
#if defined(DSP_MT_CV3_HDW)
#define DSP_MP_NEXT_MASK	0xA1A9
#endif /* defined(DSP_MT_CV1_HDW) */

/****************************************************************************************/
/*       Constants defining the time  in the frame while DSP nust not			*/
/*       be asked to sleep (RFCU interrupts phase)	 : between 500 and 550 QB	*/
/****************************************************************************************/
#define DSP_NO_SLEEP_AREA_QBC_MIN 2000
#define DSP_NO_SLEEP_AREA_QBC_MAX 2200

/*****************************************************************************************/
/*      Initialization value of the LLC timer which is initialized and decremented       */
/*      at each LLC request                                                              */
/*****************************************************************************************/
#define DSP_LLC_REQUEST_TIMER_INIT 20


/* For CV1 only, MS DSP audio module is not functionnal, so DSP_MS_NOISE_SUPRESS_FTR have to be
   deactivated !! */
#if defined(DSP_MT_CV1_HDW)
#if defined(DSP_MS_NOISE_SUPRESS_FTR)
	#error DSP_MS_NOISE_SUPRESS_FTR have to be deactivated on CV1
#endif
#endif /* DSP_MT_CV1_HDW */ 

/* For CV3 only, AU and BR DSP audio modules are in DSP bootstrap, so, if PCF5087-0, EQUALIZER_FTR
   and DSP_BR_BURST_REDUCTION_FTR have to be deactivated !! */
#if defined(DSP_MT_CV3_HDW)
#if defined(DSP_DOWNLOAD) && (defined(EQUALIZER_FTR) || defined(DSP_BR_BURST_REDUCTION_FTR))
	#error EQUALIZER_FTR and DSP_BR_BURST_REDUCTION_FTR have to be deactivated\
		when emulator is used on CV3
#endif
#endif /* DSP_MT_CV3_HDW */ 

/* == END OF INCLUDE ================================================== */
#endif

/************************************************************************/
/*         Defines for PCM samples feature                       		*/
/************************************************************************/
#if defined(DSP_MT_CV5_HDW)
#if defined(PCM_SAMPLES_FTR)

#define DSP_PCM_RECORD			0x0000
#define DSP_PCM_PLAY			0x0001
#define DSP_PCM_W_AUDIO_FTR		0x0000
#define DSP_PCM_W_NO_AUDIO_FTR		0x0001
#define DSP_PCM_CONTINIOUS_BUF		0x0000
#define DSP_PCM_FIXED_BUF		0x0001
#define DSP_PCM_FLIP_FLOP_BUF		0x0002

#endif
#endif