📄 dspdef.hec
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#define DSP_SAMPLES_MULTI_RX_NB (149)*2
#endif /* GPRS_FTR */
/*======================================================================*/
/* definition for TCH control mode parameters */
/*======================================================================*/
#define DSP_TCH_SPEECH 0
#define DSP_TCH_DATA 1
#define DSP_TCH_SIG_ONLY 2
#define DSP_TCH_HANDSET_OP 1
#define DSP_TCH_CARKIT_OP 0
#define DSP_TCH_HF_ON 1
#define DSP_TCH_HF_OFF 0
#define DSP_TCH_DTX_ON 1
#define DSP_TCH_DTX_OFF 0
#define DSP_TCH_CODEC_FR 0
#define DSP_TCH_CODEC_HR 1
#define DSP_TCH_CODEC_EFR 2
#if defined(AMR_FTR)
#define DSP_TCH_CODEC_AFS 3
#define DSP_TCH_CODEC_AHS 4
#endif
#define DSP_STOP_TCH 0
#define DSP_STOP_TCHLOOP 1
#define DSP_STOP_TCHLOOP_BBB 2
#define DSP_STOP_DAI 3
#define DSP_SPEECH_DATA_TRANSITION 6
#define DSP_FROM_TCH_TO_TCH_SAME_MODE 7
#define DSP_FROM_TCH_TO_TCH_NEW_MODE 8
#define DSP_TCH_WITHOUT_HANDOVER 9 /* used by L1 to start TCH */
/*======================================================================*/
/* definition for control mode parameters */
/*======================================================================*/
#define DSP_CONTROL_CHANNEL 0
#define DSP_CONTROL_FR 1
#define DSP_CONTROL_HR 2
#define DSP_CONTROL_DATA 3
#if defined(AMR_FTR)
#define DSP_CONTROL_AFS 4
#define DSP_CONTROL_AHS 5
#endif
/*======================================================================*/
/* definition for results arrays a_Dsp_JobRsult, a_dsp_PtrJobResult */
/*======================================================================*/
#define DSP_RET_NB_PRIO 10
/*======================================================================*/
/* Configuration of RFSIGs for DualBand: GSM or DCS configuration */
/*======================================================================*/
#ifdef RF_UAA3537_HDW
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x010
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x018
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x018
#define DSP_FROZEN_BTG_GSM850_RX_MASK 0x008
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x002
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x0
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x0
#define DSP_FROZEN_BTG_GSM850_TX_MASK 0x002
#define DSP_FROZEN_BTG_GSM_RX_VALUE 0x0
#define DSP_FROZEN_BTG_DCS_RX_VALUE 0x0
#define DSP_FROZEN_BTG_PCS_RX_VALUE 0x0
#define DSP_FROZEN_BTG_GSM850_RX_VALUE 0x0
#define DSP_FROZEN_BTG_GSM_TX_VALUE 0x0
#define DSP_FROZEN_BTG_DCS_TX_VALUE 0x0
#define DSP_FROZEN_BTG_PCS_TX_VALUE 0x0
#define DSP_FROZEN_BTG_GSM850_TX_VALUE 0x0
#else /*RF_UAA3537_HDW*/
#ifdef RADIO_3536_HDW
#if defined CELLON_PATTERN
/* begin LMSdv88743- 04/07/03 - SCH */
#if defined CR_DDTS_88743_PCS_RX_RFSIG5_HDW
/* +LMSdv94988 - 23/10/2003 - SCH */
#if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW)
/* -LMSdv94988 */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x0620
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x0620
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x0600
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x0220
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x0420
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x0420
/* +LMSdv94988 - 23/10/2003 - SCH */
#else /*if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW) */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x0023
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x0023
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x0003
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x0021
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x0022
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x0022
#endif /*if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW)*/
/* -LMSdv94988 */
#else /*CR_DDTS_88743_PCS_RX_RFSIG5_HDW*/
/* +LMSdv94988 - 23/10/2003 - SCH */
#if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW)
/* -LMSdv94988 */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x0700
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x0700
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x0600
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x0300
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x0500
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x0500
/* +LMSdv94988 - 23/10/2003 - SCH */
#else /*if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW)*/
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x0103
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x0103
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x0003
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x0101
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x0102
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x0102
#endif /*if !defined (CR_DDTS_94988_PWR_CFG_MODIFY_HDW)*/
/* -LMSdv94988 */
/* begin LMSdv88743- 04/07/03 - SCH */
#endif /*CR_DDTS_88743_PCS_RX_RFSIG5_HDW*/
/*End LMSdv88743 - 04/07/2003 */
#define DSP_FROZEN_BTG_GSM_RX_VALUE 0x0000
#define DSP_FROZEN_BTG_DCS_RX_VALUE 0x0000
#define DSP_FROZEN_BTG_PCS_RX_VALUE 0x0000
#define DSP_FROZEN_BTG_GSM_TX_VALUE 0x0000
#define DSP_FROZEN_BTG_DCS_TX_VALUE 0x0000
#define DSP_FROZEN_BTG_PCS_TX_VALUE 0x0000
#define DSP_FROZEN_BTG_GSM850_RX_MASK DSP_FROZEN_BTG_GSM_RX_MASK
#define DSP_FROZEN_BTG_GSM850_RX_VALUE DSP_FROZEN_BTG_GSM_RX_VALUE
#define DSP_FROZEN_BTG_GSM850_TX_MASK DSP_FROZEN_BTG_GSM_TX_MASK
#define DSP_FROZEN_BTG_GSM850_TX_VALUE DSP_FROZEN_BTG_GSM_TX_VALUE
#else /* CELLON_PATTERN */
#if defined EVITA
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x68
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x68
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x48
#define DSP_FROZEN_BTG_GSM850_RX_MASK DSP_FROZEN_BTG_GSM_RX_MASK
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x2A
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x61
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x65
#define DSP_FROZEN_BTG_GSM850_TX_MASK DSP_FROZEN_BTG_GSM_TX_MASK
#define DSP_FROZEN_BTG_GSM_RX_VALUE 0x68
#define DSP_FROZEN_BTG_DCS_RX_VALUE 0x68
#define DSP_FROZEN_BTG_PCS_RX_VALUE 0x48
#define DSP_FROZEN_BTG_GSM850_RX_VALUE DSP_FROZEN_BTG_GSM_RX_VALUE
#define DSP_FROZEN_BTG_GSM_TX_VALUE 0x28
#define DSP_FROZEN_BTG_DCS_TX_VALUE 0x60
#define DSP_FROZEN_BTG_PCS_TX_VALUE 0x60
#define DSP_FROZEN_BTG_GSM850_TX_VALUE DSP_FROZEN_BTG_GSM_TX_VALUE
#else /* EVITA then we are in SCALE_A1 */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0xC8
#define DSP_FROZEN_BTG_DCS_RX_MASK 0xC8
#define DSP_FROZEN_BTG_PCS_RX_MASK 0x88
#define DSP_FROZEN_BTG_GSM850_RX_MASK 0xC8
#define DSP_FROZEN_BTG_GSM_TX_MASK 0xC2
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x49
#define DSP_FROZEN_BTG_PCS_TX_MASK 0x4D
#define DSP_FROZEN_BTG_GSM850_TX_MASK 0xC2
#define DSP_FROZEN_BTG_GSM_RX_VALUE 0x00
#define DSP_FROZEN_BTG_DCS_RX_VALUE 0x00
#define DSP_FROZEN_BTG_PCS_RX_VALUE 0x40
#define DSP_FROZEN_BTG_GSM850_RX_VALUE 0x00
#define DSP_FROZEN_BTG_GSM_TX_VALUE 0x02
#define DSP_FROZEN_BTG_DCS_TX_VALUE 0x01
#define DSP_FROZEN_BTG_PCS_TX_VALUE 0x05
#define DSP_FROZEN_BTG_GSM850_TX_VALUE 0x02
#endif /* EVITA */
#endif /* SYSSOL3_CELLON_AUDIO_RADIO_HDW */
#else /* RADIO_3536_HDW */
#if !defined(RADIO_A1_IMPROVEMENT)
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x40 /*DCS_MODE FROZEN */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0x40 /*DCS_MODE FROZEN */
#define DSP_FROZEN_BTG_DCS_TX_MASK 0x80 /*EGSM_MODE FROZEN */
#define DSP_FROZEN_BTG_DCS_RX_MASK 0x80 /*EGSM_MODE FROZEN */
#define DSP_FROZEN_BTG_DCS_BITVALUE 0
#define DSP_FROZEN_BTG_GSM_BITVALUE 0
#else /* !defined(RADIO_A1_IMPROVEMENT) */
#if !defined(RADIO_A1_PLUS)
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x40 /*DCS_SW FROZEN */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0xE0 /*DCS_SW, EGSM_SW and EGSM_MODE FROZEN */
#define DSP_FROZEN_BTG_DCS_TX_MASK 0xA0 /*EGSM_SW and EGSM_MODE FROZEN*/
#define DSP_FROZEN_BTG_DCS_RX_MASK 0xE0 /*DCS_SW, EGSM_SW and EGSM_MODE FROZEN */
#define DSP_FROZEN_BTG_DCS_BITVALUE 0
#define DSP_FROZEN_BTG_GSM_BITVALUE 0
#else /* !defined(RADIO_A1_PLUS) */
#define DSP_FROZEN_BTG_GSM_TX_MASK 0x50 /*DCS_MODE et DCS_SW FROZEN */
#define DSP_FROZEN_BTG_GSM_RX_MASK 0xF0 /* All signals DCS and GSM FROZEN */
#define DSP_FROZEN_BTG_DCS_TX_MASK 0xA0 /*EGSM_MODE et EGSM_SW FROZEN */
#define DSP_FROZEN_BTG_DCS_RX_MASK 0xF0 /* All signals DCS and GSM FROZEN */
#define DSP_FROZEN_BTG_DCS_BITVALUE 0
#define DSP_FROZEN_BTG_GSM_BITVALUE 0
#endif /* !defined(RADIO_A1_PLUS) */
#endif /* !defined(RADIO_A1_IMPROVEMENT) */
#endif /* RADIO_3536_HDW */
#endif /*RF_UAA3537_HDW*/
/*======================================================================*/
/* DMA CONSTANT FOR VALIDATION TESTS */
/*======================================================================*/
#define DSP_DMA_FREE_SPACE 0x0C00
#define DSP_DMA_ADDR_IN_DSP 0x0800
#define DSP_DMA_MEMO_MASK 0x03E0
#if defined(DSP_MT_DV1_HDW)
/*======================================================================*/
/* DSP memory type needed for DMA transfer */
/*======================================================================*/
#define DSP_DMA_ID_DMEM 0
#define DSP_DMA_ID_PMEM (1<<DSP_DMA_DSP_MEMORY_OFFSET)
#endif /* DSP_MT_DV1_HDW */
#if defined(SOFT_VALID_FTR)
/*======================================================================*/
/* DSP constant for DMA ID counter setting */
/*======================================================================*/
#define DSP_DMA_TRANSFER_1 0
#define DSP_DMA_TRANSFER_2 1
#define DSP_DMA_TRANSFER_3 2
#define DSP_DMA_TRANSFER_4 3
#endif /* SOFT_VALID_FTR */
#if defined(SPEECH)
#if defined(PLAY_RECORD_AMR_FTR)
/*======================================================================*/
/* DMA ID SHELL FOR MMS RECORDING */
/*======================================================================*/
#if defined(DSP_MT_CV3_HDW)
#define DSP_DMA_MMS_REC_ID 0x0340 /* value to be changed when DSP gives the right one*/
#define DSP_DMA_MMS_PLAY_ID 0x0360 /* value to be changed when DSP gives the right one*/
#endif
#if defined(DSP_MT_CV5_HDW)
#define DSP_DMA_MMS_ID 0x0160 /* value to be changed when DSP gives the right one*/
#endif
/*======================================================================*/
/* DMA MASKS FOR MMS RECORDING */
/*======================================================================*/
#if defined(DSP_MT_CV3_HDW)
#define DSP_DMA_MMS_REC 0x0340 /* value to be changed when DSP gives the right one*/
#define DSP_DMA_MMS_PLAY 0x0360 /* value to be changed when DSP gives the right one*/
#endif
#if defined(DSP_MT_CV5_HDW)
#define DSP_DMA_MMS 0x0160 /* value to be changed when DSP gives the right one*/
#endif
#define DSP_TCH_CTRL_WORD_0_MMS 0x0003
#define DSP_MMS_MASK 0x7800
#define DSP_AMR_FILE_HEADER 0x0006
#define DSP_AMR_MAX_SPEECH_FRAME_LENGTH 0x20 /* Length in u8 */
#define DSP_AMR_BLOCK1_LENGTH DSP_AMR_FLIP_FLOP_SIZE/2 /* Length in u8 */
#define DSP_AMR_BLOCK2_LENGTH DSP_AMR_BLOCK1_LENGTH /* Length in u8 */
#define DSP_NB_OF_SPEECH_FRAMES_OFFSET 0x0001 /* Nb of speech frames before stoping the record */
/* begin LMSdv84007 - 23/04/03 - SMA */
#if defined(CR_84007)
#define DSP_AMR_BUFFER_COMMUTATION 0x0000
#define DSP_AMR_BUFFER_EMPTY 0x0001
#define DSP_AMR_PLAYBACK_COMPLETE 0x0002
#endif
/* end LMSdv84007 */
#endif /*PLAY_RECORD_AMR_FTR*/
/*======================================================================*/
/* New Voice Memo recording */
/*======================================================================*/
/*
-------------------------------------------------------------------
| b15 | b14 : b13 | b12 | b11 | b10 | b9 | b6 : b8 | b5 | b0 : b4 |
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