dspdef.hec

这是用Labwindows开发的一个RF test程序。 用于日本机种的组装后ANT 测试。

/******************************************************************************/
/* SCCS: %Z% Name: %M% Date US: %G% %U% Ver.: %I% */
/******************************************************************************/
/*F(*************************************************************************** 
 * File name : dspdef.hec
 * Project :   
 * Module :    DSP
 * Date : (US) %G% %U%
 * Version : %I%
 * Compiler name and release(s) :
 *----------------------------------------------------------------------------* 
 *----------------------------------------------------------------------------* 
 *                                    DESCRIPTION
 *
 *----------------------------------------------------------------------------* 
 *----------------------------------------------------------------------------* 
 *                           FUNCTIONS DEFINED IN THIS FILE
 *----------------------------------------------------------------------------* 
 * Name            | Object
 *----------------------------------------------------------------------------* 
 * 
 *----------------------------------------------------------------------------* 
 *----------------------------------------------------------------------------* 
 *                                    EVOLUTION
 *----------------------------------------------------------------------------* 
 * Date     | Author    | Arnb   | Description
 *----------------------------------------------------------------------------* 
 * 02-09-97 | O.VOGT    |        | Creation from DSP-1.2                      *
 * 03-07-98 | P.HERVIEU |	 | Update for MT			      *
 ***************************************************************************)F*/
#ifndef DSPDEF_HEC
#define DSPDEF_HEC

/*======================================================================*/
/* Somes general defines concerning FCB/SCB/FREQ			*/
/*======================================================================*/
#define DSP_START_SCH_ANTICIPATION     34


/*======================================================================*/
/* constant used by DPWS before going to sleep to test if the SPI is    */
/* full of a dsp error							*/
/*======================================================================*/
#define DSP_MSG_ERROR_RETURNED  0xFF03 

#if defined(DSP7MISC_C)
#if (DSP_MSG_ERROR_RETURNED&0xFF00) != DSP_MSG_ERROR 
	#error DSP_MSG_ERROR_RETURNED is not equal to DSP_MSG_ERROR
#endif 
#endif

/*======================================================================*/
/* Define for Id Job management                                         */
/*======================================================================*/
/* Shift for ERP */
#define DSP_ERP_QUEUE_SHIFT	4	/* ERP extracted from queue id */

/* Shift for TS_inter */
#define DSP_HWL_COUNTER_SHIFT	8	/* TS_inter extracted from queue id */

/* State Number of dsp_Readxxx functions                                */
#define DSP_FINAL_STATE_READ_FUNCTION   (0<<5)
#define DSP_STATE_ONE_READ_FUNCTION     (1<<5)
#define DSP_STATE_TWO_READ_FUNCTION     (2<<5)
#define DSP_STATE_THREE_READ_FUNCTION   (3<<5)
#define DSP_STATE_FOUR_READ_FUNCTION    (4<<5)
#define DSP_DBG_STATE_READ_FUNCTION     (5<<5)

/* The HWL counter is incremented in MC_DSP_CTRL_UPDATE_JOBID.          */

/*======================================================================*/
/* RADIO RESSOURCE DESCRIPTION : BURST TYPE 				*/
/*======================================================================*/
#define DSP_BURST_WFUR		0
#define DSP_BURST_WFUR2		2
#define DSP_BURST_RX_NB		4
#define DSP_BURST_RX_SCH	6
#define DSP_BURST_RX_FCH	8
#define DSP_BURST_OFF_MEAS	10
#define DSP_BURST_RX_NB_ADC	12
#define DSP_BURST_RX_PWR	14
#define DSP_BURST_RX_NB_1       16
#define DSP_BURST_RX_NB_2	18
#define DSP_BURST_RX_NB_3	20
#define DSP_BURST_RX_NB_4       22
#define DSP_BURST_RX_NB_5	24
#define DSP_BURST_RX_NB_6	26
#define DSP_BURST_RX_NB_7       28
#define DSP_BURST_RX_NB_8       30
#define DSP_BURST_TX_NB		32
#define DSP_BURST_TX_AB		34
#define DSP_BURST_TX_NB_RAMP	36
#define DSP_BURST_TX_AB_RAMP	38
#define DSP_BURST_TX_NB_1	40
#define DSP_BURST_TX_NB_2	42
#if !defined(HWL_4TX_FTR)
#define DSP_BURST_RX_FCB_START	44
#define DSP_BURST_RX_FCB_CONT	46
#define DSP_BURST_RX_FCB_STOP	48
#define DSP_BURST_RX_PWR_PAGING	50
#else /* HWL_4TX_FTR */
#define DSP_BURST_TX_NB_3	44
#define DSP_BURST_TX_NB_4	46
#define DSP_BURST_RX_FCB_START	48
#define DSP_BURST_RX_FCB_CONT	50
#define DSP_BURST_RX_FCB_STOP	52
#define DSP_BURST_RX_PWR_PAGING	54
#endif /* HWL_4TX_FTR */


/*======================================================================*/
/* defines for FREQBAND mode						*/
/*======================================================================*/
#define GSM_BAND	0x1
#define EGSM_BAND	0x2
#define DCS_BAND	0x4
#define PCS_BAND	0x8
#define GSM850_BAND	0x10

#define DSP_GSM_RANGE 5

#if defined(RADIO_PA_FREQ_COMPENSATION_HDW) && defined(PA_FREQ_COMPENSATION_HDW)
#ifdef __TRIBAND__
#define DSP_MASK_PCS1900 0x8000 /* = MASK_PCS1900 defined in l1a.hec */
#endif
#endif

/*======================================================================*/
/* defines for CmiBuffId mode						*/
/*======================================================================*/
#define TCH_BUFF 0x0
#define CCH_BUFF 0x1
#define A_BUFF 0x2
#define B_BUFF 0x3
#define C_BUFF 0x4

#define DSP_TCH_BUFFER 0x0
#define DSP_CCH_BUFFER 0x1

/*======================================================================*/
/* defines for Access_Type						*/
/*======================================================================*/
#define RANDOM_8B 0
#define RANDOM_11 1

#if defined(GPRS_FTR)
/*======================================================================*/
/* defines for BitField_Rx						*/
/*======================================================================*/
#define DWLBURST	0x1
#define DWL_USF_BURST 	0x2
#define NO_DWL_BURST 	0x0
#define DUMMY_BURST     0x3


/*======================================================================*/
/* defines for BitField_Tx						*/
/*======================================================================*/
#define NO_UPBURST 			0x0


#define USF_UPBURST			0x0B00  
/* in dynamic or extended dynamic, the slot precised with this value
is USF dependent, WITH the corresponding RX on the same slot, 
the TX is sent if the USF is matching   */

#if defined(PR_76215)
#define USF_UPBURST_TEST_MODE		0x0A00  
/* Specific for DBLER test with multi slot on Tx
Similar to USF_UPBURST but without shifting ressource.
Rx on a TS => Tx on the same TS		*/
#endif

#define USF_UPBURST_NO_RX		0x0300 
/* in dynamic or extended dynamic, the slot precised with this value
is USF dependent, WITHOUT the corresponding RX on the same slot, 
the TX is SENT if the USF is matching   */

#if defined(PR_76215)
#define USF_UPBURST_NO_RX_TEST_MODE	0x0200 
/* Specific for DBLER test with multi slot on Tx
Similar to USF_UPBURST_NO_RX_TEST_MODE but without shifting ressource.
Rx on a TS => Tx on the same TS		*/
#endif

#define USF_UPBURST_RX_NO_TX    	0x0800
/* in dynamic or extended dynamic, the slot precised with this value
is USF dependent, WITH the corresponding RX on the same slot, 
the TX is NOT SENT even if the USF is matching   */

#define MANDATORY_UPBURST 		0x400
/* in fixed allocation and class12 extended dynamic, the slot precised with this value is mandatory AND NORMAL BURST, then the TX is SENT, there is NO corresponding RX on the same slot */

#define MANDATORY_8BIT_RANDOM 		0x8400
/* in fixed allocation only, the slot precised with this value
is mandatory AND ACCESS BURST ON 8 BITS, then the TX is SENT, there is NO corresponding RX on the same slot */

#define MANDATORY_11BIT_RANDOM 		0xC400
/* in fixed allocation only, the slot precised with this value
is mandatory AND ACCESS BURST ON 11 BITS, then the TX is SENT, there is NO corresponding RX on the same slot */



#define MAND_UPBURST_WITH_RX                0x0C00
/* in dynamic or extended dynamic, the slot precised with this value
is mandatory AND NORMAL BURST, WITH the corresponding RX on the same slot*/

#define MAND_UPBURST_WITH_RX_8BIT_RANDOM    0x8C00
/* in dynamic or extended dynamic, the slot precised with this value
is mandatory AND ACCESS BURST ON 8 BITS, WITH the corresponding RX on the same slot*/

#define MAND_UPBURST_WITH_RX_11BIT_RANDOM   0xCC00
/* in dynamic or extended dynamic, the slot precised with this value
is mandatory AND ACCESS BURST ON 11 BITS, WITH the corresponding RX on the same slot*/


#define DSP_RACH_ID		0xFFFF

/*======================================================================*/
/* defines for TranferMode						*/
/*======================================================================*/
#define GSM_MODE	DSP_MP_USF_MODE_GSM
#define GPRS_FIXED	DSP_MP_USF_MODE_FIXED
#define GPRS_DYN	DSP_MP_USF_MODE_DYN
#define GPRS_EXT_DYN	DSP_MP_USF_MODE_EXT_DYN
#define GPRS_FULL_PCCCH 0x10
#define DSP_GPRS_TRANSFER_MASK 0x0F

#endif /* GPRS_FTR */

/*======================================================================*/
/* defines for TS_nb DSP7_2CtrlSetTxPower to distinguish ramp		*/
/* computation for normal burst and random burst			*/
/*======================================================================*/
#define RACH_TX 8

#if defined(GPRS_FTR)
/*======================================================================*/
/*  definition for GPRS PDTCH control mode parameters			*/
/*======================================================================*/
#define DSP_FROM_PDTCH_IDLE 1
#define DSP_FROM_PDTCH_TO_PDTCH 2
#endif /* GPRS_FTR */

/*======================================================================*/
/* Some Miscallenous defines                                            */
/*======================================================================*/
/* define for the DSP7_0InitAll function                                */
#define DSP_RESET_ON_SWITCH_ON      0
#define DSP_RESET_ON_WAKE_UP        1
#define DSP_RESET_ON_DOUBLE_IDLE    2
#define DSP_RECONF_LIGHT	    3

/* Transmit mode 							*/
#define DSP_NB_MODE                 0 
#define DSP_AB_MODE                 3 

/* Returned messages 							*/
#define DSP_SCI_RETURN               1
#define DSP_NO_SCI_RETURN            0

/*======================================================================*/
/* Define for Id Job management                                         */
/*======================================================================*/
/* Definition of the Id Job mask:                                              
   ------------------------------------------------------------------------
  |           HWL counter         |      State     | ERP |      Queue      |   
   ------------------------------------------------------------------------
  b15                           b8 b7            b5   b4  b3               b0
									*/

#define DSP_RXDECOD_QUEUE                 0x0 /* Decode executed on EOB it */
#define DSP_TXENCOD_QUEUE                 0x1 /* Encode executed on BB it */
#define DSP_FOREGD_QUEUE                  0x2 /* For TDMA treatments */

#define DSP_AUDIO_QUEUE                   0x3
#define DSP_BACKGD_QUEUE		  0x3 

#define DSP_DMA_QUEUE			  0x4 

#define DSP_FOREGD_RF_QUEUE		  0x5

#if defined(TEST_HWL)
#define DSP_LLC_BACKGD_QUEUE              0x7 /* For LLC treatments */
#define DSP_NO_WAIT_FOR_JOB               0x8 /* when no expected return */
#else

#if defined(AMR_FTR) /* for CV3 */
#define DSP_NO_WAIT_FOR_JOB               0x7
#else /* for CV1 */
#define DSP_NO_WAIT_FOR_JOB               0x6
#endif /* AMR_FTR */
#endif /* TEST_HWL */

#if defined(AMR_FTR)
#define DSP_AUDIO_DL_QUEUE                0x3
#define DSP_AUDIO_UL_QUEUE                0x6

/* DUMMY_QUEUE define for AMR because of two queues for AMR return :
DSP_AUDIO_DL_QUEUE and DSP_AUDIO_UL_QUEUE
The right AUDIO_QUEUE is set in DSP0_4ResultTreatement at
DSP_CM_DEC_TCH_INFO or DSP_CM_ENC_TCH_INFO returns */          

#define DSP_DUMMY_QUEUE			  0x0F 
#endif /* AMR_FTR */ 

/*======================================================================*/
/*  REAL REGISTERS                                                      */
/*======================================================================*/

/* PARALLEL INPUT REGISTER                                              */
#define SPI_reg		PCF508x_SPI

/* PARALLEL OUTPUT REGISTER                                             */
#define SPO_reg		PCF508x_SPO

/* I/O STATUS REGISTER                                                  */