reg5087.ho

这是用Labwindows开发的一个RF test程序。 用于日本机种的组装后ANT 测试。

#define IID_MASK	  0x1F 				/* Identification Mask 		*/
#define IID_DMA_IIC_STAT  0x1C				/* DMA IIC STATUS Interrupt 	*/
#define IID_DMA_SIM_STAT  0x1B				/* DMA SIM STATUS Interrupt 	*/
#define IID_DMA_UART0_RX  0x1A				/* DMA UART0 RECEIVE Interrupt  */
#define IID_DMA_UART0_TX  0x19				/* DMA UART0 TRANSMIT Interrupt */
#define IID_DMA_UART1_RX  0x17				/* DMA UART1 RECEIVE Interrupt 	*/
#define IID_DMA_UART1_TX  0x16				/* DMA UART1 TRANSMIT Interrupt */
#define NMI		  0xF				/* Non Maskable Interrupt 	*/
#define IID_FRAME	  0xE				/* FRAME Interrupt 		*/
#define IID_DSP_REQ	  0xD				/* DSP REQ Interrupt 		*/
#define IID_IIC_STAT	  0xC				/* IIC STATUS Interrupt 	*/
#define IID_SIM_STAT	  0xB				/* SIM STATUS Interrupt 	*/
#define IID_UART0_RX	  0xA				/* UART0 RECEIVE Interrupt 	*/
#define IID_UART0_TX	  9			  	/* UART0 TRANSMIT Interrupt 	*/
#define IID_UART0_STAT    8 				/* UART0 STATUS Interrupt 	*/
#define IID_UART1_RX	  7				/* UART1 RECEIVE Interrupt 	*/
#define IID_UART1_TX	  6				/* UART1 TRANSMIT Interrupt 	*/
#define IID_UART1_STAT    5 				/* UART1 STATUS Interrupt 	*/
#define IID_TIM_INT	  4 				/* TIMER Interrupt 		*/
#define IID_KBS		  3 				/* KEYBOARD SCANNER Interrupt 	*/
#define IID_ON_OFF_STAT	  2				/* ON_OFF Interrupt 		*/
#define IID_EXT_1	  1				/* EXTERNAL1 Interrupt 		*/
#define IID_EXT_2	  0 				/* EXTERNAL2 Interrupt 		*/


/* PIR */

#define ALL_CLEARED     ( 0x0000)       /* clear all pending interrupts */
#define	PIR0		( BIT0  )	/* 0* = no pendig interrupt */
		       	      		/* 1  = pending interrupt for pin INT0 */
#define	PIR1		( BIT1  )      	/* 0* = no pendig interrupt */
			       		/* 1  = pending interrupt for pin INT1 */
#define	PIR2		( BIT2  )       /* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT2 */
#define	PIR3		( BIT3  )     	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT3 */
#define	PIR4		( BIT4  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT4 */
#define	PIR5		( BIT5  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT5 */
#define	PIR6		( BIT6  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT6 */
#define	PIR7		( BIT7  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT7 */
#define	PIR8		( BIT8  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT8 */
#define	PIR9		( BIT9  )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT9 */
#define	PIR10		( BIT10 )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT10 */
#define	PIR11		( BIT11 )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT11 */
#define	PIR12		( BIT12 )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT12 */
#define	PIR13		( BIT13 )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT13 */
#define	PIR14		( BIT14 )      	/* 0* = no pendig interrupt */
					/* 1  = pending interrupt for pin INT14 */
#define	PIR15		( BIT15 )	/* 0* = no pendig interrupt */
                                        /* 1  = pending interrupt for pin INT15 */


/* ICR */

#define ALL_IRQ		0xFFFF		/* all interrupt on IRQ			   */
#define	ICR0		( BIT0  )	/* 1 = Interrupt Int0  is connected to IRQ 
					   0 = Interrupt Int0  is connected to FIQ */
#define	ICR1		( BIT1  )	/* 1 = Interrupt Int1  is connected to IRQ 
					   0 = Interrupt Int1  is connected to FIQ */
#define	ICR2		( BIT2  )	/* 1 = Interrupt Int2  is connected to IRQ 
					   0 = Interrupt Int2  is connected to FIQ */
#define	ICR3		( BIT3  )	/* 1 = Interrupt Int3  is connected to IRQ 
					   0 = Interrupt Int3  is connected to FIQ */
#define	ICR4		( BIT4  )	/* 1 = Interrupt Int4  is connected to IRQ 
					   0 = Interrupt Int4  is connected to FIQ */
#define	ICR5		( BIT5  )	/* 1 = Interrupt Int5  is connected to IRQ 
					   0 = Interrupt Int5  is connected to FIQ */
#define	ICR6		( BIT6  )	/* 1 = Interrupt Int6  is connected to IRQ 
					   0 = Interrupt Int6  is connected to FIQ */
#define	ICR7		( BIT7  )	/* 1 = Interrupt Int7  is connected to IRQ 
					   0 = Interrupt Int7  is connected to FIQ */
#define	ICR8		( BIT8  )	/* 1 = Interrupt Int8  is connected to IRQ 
					   0 = Interrupt Int8  is connected to FIQ */
#define	ICR9		( BIT9  )	/* 1 = Interrupt Int9  is connected to IRQ 
					   0 = Interrupt Int9  is connected to FIQ */
#define	ICR10		( BIT10 )	/* 1 = Interrupt Int10 is connected to IRQ 
					   0 = Interrupt Int10 is connected to FIQ */
#define	ICR11		( BIT11 )	/* 1 = Interrupt Int11 is connected to IRQ 
			        	   0 = Interrupt Int11 is connected to FIQ */
#define	ICR12		( BIT12 )	/* 1 = Interrupt Int12 is connected to IRQ 
					   0 = Interrupt Int12 is connected to FIQ */
#define	ICR13		( BIT13 )	/* 1 = Interrupt Int13 is connected to IRQ 
					   0 = Interrupt Int13 is connected to FIQ */
#define	ICR14		( BIT14 )	/* 1 = Interrupt Int14 is connected to IRQ 
					   0 = Interrupt Int14 is connected to FIQ */
#define	ICR15		( BIT15 )	/* 1 = Interrupt Int15 is connected to IRQ 
					   0 = Interrupt Int15 is connected to FIQ */



															 
/**********************************************************************/

 /*----------*/
 /* SIM UNIT */
 /*----------*/

#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_SICR0	*( ( volatile u16 *) ( 0xFFFF9202) )   /* SIM_CTRL interrupt control register 0 */
#endif

#define SIMU_TEN    	     ( BIT0  )		     /* Transmitter enable */
#define SIMU_REN	     ( BIT1  )		     /* Receiver enable */
#define SIMU_BRC0	     ( BIT2  )		     /* Baudrate control BRC0 */
#define SIMU_BRC1	     ( BIT3  )		     /* Baudrate control BRC1 */
#define SIMU_BRC2	     ( BIT4  )		     /* Baudrate control BRC2 */
#define SIMU_FCON	     ( BIT5  )		     /* Force Convention (clear CONV, VCON status bits) */
#define SIMU_WWTEN	     ( BIT6  )		     /* Work waiting time enable */
#define SIMU_EBC0	     ( BIT7  )		     /* Error bits */
#define SIMU_EBC1	     ( BIT8  )		     /* Error bits */
#define SIMU_FI	             ( BIT9  )		     /* Work Waiting Time clockrate conversion factor */
#define SIMU_FTPE	     ( BIT10 )		     /* Force transmit parity error (for test only) */
#define SIMU_FRPE	     ( BIT11 )		     /* Force receive parity error (for test only) */



#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_SISR0	*( ( volatile u16 *) ( 0xFFFF9206) )   /* SIM_CTRL interrupt status register 0 */
#endif

#define SIMU_TDRE            ( BIT0  )		      /* Transmit data register empty */
#define SIMU_RDRF            ( BIT1  )		      /* Receive data register full */
#define SIMU_PE              ( BIT2  )		      /* Parity error (receive error) */
#define SIMU_OV              ( BIT3  )		      /* Overrun error (receive error) */
#define SIMU_WTO             ( BIT4  )		      /* Work waiting time - timeout */
#define SIMU_CONV            ( BIT5  )		      /* Convention status */
#define SIMU_VCON            ( BIT6  )		      /* Convention valid */
#define SIMU_SERR            ( BIT7  )		      /* Error bit for external SIMERR line */
#define SIMU_NACK            ( BIT8  )		      /* Negative acknolwledge (transmit error) */


#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_SIRXO	*( ( volatile u8 *)  ( 0xFFFF920B) )   /* SIM_CTRL receive register */
#define PCF5087_SITXI	*( ( volatile u8 *)  ( 0xFFFF920F) )   /* SIM_CTRL transmit register */
#define PCF5087_SIUPSR0	*( ( volatile u8 *)  ( 0xFFFF9213) )   /* SIM_CTRL prescaler register 0 */
#define PCF5087_SISPVR0	*( ( volatile u8 *)  ( 0xFFFF9217) )   /* SIM_CTRL supervision register 0 */
#endif

/**********************************************************************/


/*----------*/
/* PWM UNIT */
/*----------*/
#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_PWMP	*( ( volatile u16 *) (0xFFFF8702) )   /* Prescaler Frequency Control Register */
#define PCF5087_PWM0	*( ( volatile u8  *) (0xFFFF8707) )   /* PWM 0                                */
#define PCF5087_PWM1	*( ( volatile u8  *) (0xFFFF870B) )   /* PWM 1                                */
#endif


/**********************************************************************/

/*----------*/
/* DMA UNIT */
/*----------*/


#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_UA0TXCNTRLSTAT	*( ( volatile u16 *) ( 0xFFFF8202) )   /* UART0 tx control status register */
#define PCF5087_UA0TXCNTRLSTATADDR 0xFFFF8202
#define PCF5087_UA0TXCNT	*( ( volatile u16 *) ( 0xFFFF8206) )   /* UART0 tx byte count register */
#define PCF5087_UA0TXPOINT	*( ( volatile u32 *) ( 0xFFFF8208) )   /* UART0 tx ext. memory read pointer */

/* Because of the bug concerning bit SHEN, u32 registers must be written with two 16-bit accesses*/
#if defined(BUG_SHEN)
#define PCF5087_UA0TXPOINT_LOW  *( ( volatile u16 *) ( 0xFFFF8208) )
#define PCF5087_UA0TXPOINT_HIGH *( ( volatile u16 *) ( 0xFFFF820A) )
#endif /* BUG_SHEN */

#define PCF5087_UA0RXCNTRLSTAT	*( ( volatile u16 *) ( 0xFFFF8212) )   /* UART0 rx control status register */
#define PCF5087_UA0RXCNTRLSTATADDR 0xFFFF8212
#define PCF5087_UA0RXCNT	*( ( volatile u16 *) ( 0xFFFF8216) )   /* UART0 rx byte count register */
#define PCF5087_UA0RXPOINT	*( ( volatile u32 *) ( 0xFFFF8218) )   /* UART0 rx ext. memory write pointer */

/* Because of the bug concerning bit SHEN, u32 registers must be written with two 16-bit accesses*/
#if defined(BUG_SHEN)
#define PCF5087_UA0RXPOINT_LOW  *( ( volatile u16 *) ( 0xFFFF8218) )
#define PCF5087_UA0RXPOINT_HIGH *( ( volatile u16 *) ( 0xFFFF821A) )
#endif /* BUG_SHEN */

#define PCF5087_UA1TXCNTRLSTAT	*( ( volatile u16 *) ( 0xFFFF8222) )   /* UART1 tx control status register */
#define PCF5087_UA1TXCNTRLSTATADDR 0xFFFF8222
#define PCF5087_UA1TXCNT	*( ( volatile u16 *) ( 0xFFFF8226) )   /* UART1 tx byte count register */
#define PCF5087_UA1TXPOINT	*( ( volatile u32 *) ( 0xFFFF8228) )   /* UART1 tx ext. memory read pointer */

/* Because of the bug concerning bit SHEN, u32 registers must be written with two 16-bit accesses*/
#if defined(BUG_SHEN)
#define PCF5087_UA1TXPOINT_LOW  *( ( volatile u16 *) ( 0xFFFF8228) )
#define PCF5087_UA1TXPOINT_HIGH *( ( volatile u16 *) ( 0xFFFF822A) )
#endif /* BUG_SHEN */

#define PCF5087_UA1RXCNTRLSTAT	*( ( volatile u16 *) ( 0xFFFF8232) )   /* UART1 rx control status register */
#define PCF5087_UA1RXCNTRLSTATADDR 0xFFFF8232
#define PCF5087_UA1RXCNT	*( ( volatile u16 *) ( 0xFFFF8236) )   /* UART1 rx byte count register */
#define PCF5087_UA1RXPOINT	*( ( volatile u32 *) ( 0xFFFF8238) )   /* UART1 rx ext. memory write pointer */

/* Because of the bug concerning bit SHEN, u32 registers must be written with two 16-bit accesses*/
#if defined(BUG_SHEN)
#define PCF5087_UA1RXPOINT_LOW  *( ( volatile u16 *) ( 0xFFFF8238) )
#define PCF5087_UA1RXPOINT_HIGH *( ( volatile u16 *) ( 0xFFFF823A) )
#endif /* BUG_SHEN */

#define PCF5087_SIMCNTRLSTAT	*( ( volatile u16 *) ( 0xFFFF8242) )   /* SIM control status register */
#define PCF5087_SIMCNTRLSTATADDR 0xFFFF8242
#define PCF5087_SIMCNT	        *( ( volatile u16 *) ( 0xFFFF8246) )   /* SIM byte count register */
#define PCF5087_SIMPOINT	*( ( volatile u32 *) ( 0xF