📄 reg5087.ho
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#define DSPCLK_26MHZ ( BIT13 )
#define DSPCLK_13MHZ ( BIT14 )
#define DSPCLK_6_5MHZ ( BIT14 | BIT13 )
/**********************************************************************/
/*----------*/
/* ICU UNIT */
/*----------*/
#if defined (__arm) || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_SETINT *( ( volatile u16 *) (0xFFFF812E) ) /* Reserved - Test register */
#define PCF5087_IMR *( ( volatile u8 *) (0xFFFF8117) ) /* Interrupt Mask Register */
#define PCF5087_EBA *( ( volatile u32 *) (0xFFFF8118) ) /* Exception Base Address */
#define PCF5087_IID_FIQ *( ( volatile u8 *) (0xFFFF811F) ) /* FIQ Interrupt identification register */
#define PCF5087_IID_IRQ *( ( volatile u8 *) (0xFFFF8123) ) /* IRQ Interrupt identification register */
#define PCF5087_PIR *( ( volatile u16 *) (0xFFFF8126) ) /* Pending Interrupt Register */
#define PCF5087_ICR *( ( volatile u16 *) (0xFFFF812A) ) /* Interrupt Configuration Register */
#define PCF5087_IER *( ( volatile u16 *) (0xFFFF8102) ) /* interrupt enable register */
#define PCF5087_LIR0 *( ( volatile u16 *) (0xFFFF8106) ) /* Latched Interrupt Register 0 */
#define PCF5087_LIR1 *( ( volatile u16 *) (0xFFFF810A) ) /* Latched Interrupt Register 1 */
#define PCF5087_LIR2 *( ( volatile u16 *) (0xFFFF810E) ) /* Latched Interrupt Register 2 */
#define PCF5087_LIR3 *( ( volatile u16 *) (0xFFFF8112) ) /* Latched Interrupt Register 3 */
#endif
/* IER */
#define ALL_DISABLED ( 0x0000) /* disable all interrupts */
#define EXT2 ( BIT0 ) /* external interrupt 2 */
#define EXT1 ( BIT1 ) /* external interrupt 1 */
#define ON_OFF ( BIT2 ) /* ON OFF logic interrupt */
#define KBS ( BIT3 ) /* keyboard sacnner interrupt */
#define TIM_INT ( BIT4 ) /* SCTU timer interrupt */
#define UART1_STAT ( BIT5 ) /* UART1 status interrupt */
#define UART1_TX ( BIT6 ) /* UART1 transmit interrupt */
#define UART1_RX ( BIT7 ) /* UART1 receive interrupt */
#define UART0_STAT ( BIT8 ) /* UART0 status interrupt */
#define UART0_TX ( BIT9 ) /* UART0 transmit interrupt */
#define UART0_RX ( BIT10 ) /* UART0 receive interrupt */
#define SIM_STAT ( BIT11 ) /* SIMU status interrupt */
#define IIC_STAT ( BIT12 ) /* IIC status interrupt */
#define DSP_REQ ( BIT13 ) /* PIO read/write request interrupt */
#define FRAME ( BIT14 ) /* frame interrupt*/
#define WAKE_UP ( BIT15 ) /* Wake Up interrupt */
#define CLEAR_PIR0 0x8880 /* Be careful when clearing pending interrupt flag */
#define CLEAR_PIR1 0x8808 /* For example : */
#define CLEAR_PIR2 0x8088 /* PCF508x_LIR1 &= ~PIR4; must NOT be used */
#define CLEAR_PIR3 0x0888 /* interrupts can be lost if the pending flag is */
#define CLEAR_PIR4 0x8880 /* set by hardware between the reading and writing */
#define CLEAR_PIR5 0x8808 /* of the LIR register. */
#define CLEAR_PIR6 0x8088 /* To avoid this, use : */
#define CLEAR_PIR7 0x0888 /* PCF508x_LIR1=(PCF508x_LIR1 & ~PIR4)|CLEAR_PIR4; */
#define CLEAR_PIR8 0x8880
#define CLEAR_PIR9 0x8808
#define CLEAR_PIR10 0x8088
#define CLEAR_PIR11 0x0888
#define CLEAR_PIR12 0x8880
#define CLEAR_PIR13 0x8808
#define CLEAR_PIR14 0x8088
#define CLEAR_PIR15 0x0888
/* LIR */
#define IPL0_7 ( BIT2 | BIT1 | BIT0 ) /* 111 = priority level 7 for pin INT0 (higher priority) */
#define IPL0_6 ( BIT2 | BIT1 ) /* 110 = priority level 6 for pin INT0 */
#define IPL0_5 ( BIT2 | BIT0 ) /* 101 = priority level 5 for pin INT0 */
#define IPL0_4 ( BIT2 ) /* 100 = priority level 4 for pin INT0 */
#define IPL0_3 ( BIT1 | BIT0 ) /* 011 = priority level 3 for pin INT0 */
#define IPL0_2 ( BIT1 ) /* 010 = priority level 2 for pin INT0 */
#define IPL0_1 ( BIT0 ) /* 001 = priority level 1 for pin INT0 (lower priority) */
#define IPL0_0 ZEROS /* 000 = priority level 0 for pin INT0 (interrupt disabled) */
#define IPL1_7 ( BIT6 | BIT5 | BIT4 ) /* 111 = priority level 7 for pin INT1 (higher priority) */
#define IPL1_6 ( BIT6 | BIT5 ) /* 110 = priority level 6 for pin INT1 */
#define IPL1_5 ( BIT6 | BIT4 ) /* 101 = priority level 5 for pin INT1 */
#define IPL1_4 ( BIT6 ) /* 100 = priority level 4 for pin INT1 */
#define IPL1_3 ( BIT5 | BIT4 ) /* 011 = priority level 3 for pin INT1 */
#define IPL1_2 ( BIT5 ) /* 010 = priority level 2 for pin INT1 */
#define IPL1_1 ( BIT4 ) /* 001 = priority level 1 for pin INT1 (lower priority) */
#define IPL1_0 ZEROS /* 000 = priority level 0 for pin INT1 (interrupt disabled) */
#define IPL2_7 ( BIT10 | BIT9 | BIT8 ) /* 111 = priority level 7 for pin INT2 (higher priority) */
#define IPL2_6 ( BIT10 | BIT9 ) /* 110 = priority level 6 for pin INT2 */
#define IPL2_5 ( BIT10 | BIT8 ) /* 101 = priority level 5 for pin INT2 */
#define IPL2_4 ( BIT10 ) /* 100 = priority level 4 for pin INT2 */
#define IPL2_3 ( BIT9 | BIT8 ) /* 011 = priority level 3 for pin INT2 */
#define IPL2_2 ( BIT9 ) /* 010 = priority level 2 for pin INT2 */
#define IPL2_1 ( BIT8 ) /* 001 = priority level 1 for pin INT2 (lower priority) */
#define IPL2_0 ZEROS /* 000 = priority level 0 for pin INT2 (interrupt disabled) */
#define IPL3_7 ( BIT14 | BIT13 | BIT12 ) /* 111 = priority level 7 for pin INT3 (higher priority) */
#define IPL3_6 ( BIT14 | BIT13 ) /* 110 = priority level 6 for pin INT3 */
#define IPL3_5 ( BIT14 | BIT12 ) /* 101 = priority level 5 for pin INT3 */
#define IPL3_4 ( BIT14 ) /* 100 = priority level 4 for pin INT3 */
#define IPL3_3 ( BIT13 | BIT12 ) /* 011 = priority level 3 for pin INT3 */
#define IPL3_2 ( BIT13 ) /* 010 = priority level 2 for pin INT3 */
#define IPL3_1 ( BIT12 ) /* 001 = priority level 1 for pin INT3 (lower priority) */
#define IPL3_0 ZEROS /* 000 = priority level 0 for pin INT3 (interrupt disabled) */
#define IPL4_7 ( BIT2 | BIT1 | BIT0 ) /* 111 = priority level 7 for pin INT4 (higher priority) */
#define IPL4_6 ( BIT2 | BIT1 ) /* 110 = priority level 6 for pin INT4 */
#define IPL4_5 ( BIT2 | BIT0 ) /* 101 = priority level 5 for pin INT4 */
#define IPL4_4 ( BIT2 ) /* 100 = priority level 4 for pin INT4 */
#define IPL4_3 ( BIT1 | BIT0 ) /* 011 = priority level 3 for pin INT4 */
#define IPL4_2 ( BIT1 ) /* 010 = priority level 2 for pin INT4 */
#define IPL4_1 ( BIT0 ) /* 001 = priority level 1 for pin INT4 (lower priority) */
#define IPL4_0 ZEROS /* 000 = priority level 0 for pin INT4 (interrupt disabled) */
#define IPL5_7 ( BIT6 | BIT5 | BIT4 ) /* 111 = priority level 7 for pin INT5 (higher priority) */
#define IPL5_6 ( BIT6 | BIT5 ) /* 110 = priority level 6 for pin INT5 */
#define IPL5_5 ( BIT6 | BIT4 ) /* 101 = priority level 5 for pin INT5 */
#define IPL5_4 ( BIT6 ) /* 100 = priority level 4 for pin INT5 */
#define IPL5_3 ( BIT5 | BIT4 ) /* 011 = priority level 3 for pin INT5 */
#define IPL5_2 ( BIT5 ) /* 010 = priority level 2 for pin INT5 */
#define IPL5_1 ( BIT4 ) /* 001 = priority level 1 for pin INT5 (lower priority) */
#define IPL5_0 ZEROS /* 000 = priority level 0 for pin INT5 (interrupt disabled) */
#define IPL6_7 ( BIT10 | BIT9 | BIT8 ) /* 111 = priority level 7 for pin INT6 (higher priority) */
#define IPL6_6 ( BIT10 | BIT9 ) /* 110 = priority level 6 for pin INT6 */
#define IPL6_5 ( BIT10 | BIT8 ) /* 101 = priority level 5 for pin INT6 */
#define IPL6_4 ( BIT10 ) /* 100 = priority level 4 for pin INT6 */
#define IPL6_3 ( BIT9 | BIT8 ) /* 011 = priority level 3 for pin INT6 */
#define IPL6_2 ( BIT9 ) /* 010 = priority level 2 for pin INT6 */
#define IPL6_1 ( BIT8 ) /* 001 = priority level 1 for pin INT6 (lower priority) */
#define IPL6_0 ZEROS /* 000 = priority level 0 for pin INT6 (interrupt disabled) */
#define IPL7_7 ( BIT14 | BIT13 | BIT12 ) /* 111 = priority level 7 for pin INT7 (higher priority) */
#define IPL7_6 ( BIT14 | BIT13 ) /* 110 = priority level 6 for pin INT7 */
#define IPL7_5 ( BIT14 | BIT12 ) /* 101 = priority level 5 for pin INT7 */
#define IPL7_4 ( BIT14 ) /* 100 = priority level 4 for pin INT7 */
#define IPL7_3 ( BIT13 | BIT12 ) /* 011 = priority level 3 for pin INT7 */
#define IPL7_2 ( BIT13 ) /* 010 = priority level 2 for pin INT7 */
#define IPL7_1 ( BIT12 ) /* 001 = priority level 1 for pin INT7 (lower priority) */
#define IPL7_0 ZEROS /* 000 = priority level 0 for pin INT7 (interrupt disabled) */
#define IPL8_7 ( BIT2 | BIT1 | BIT0 ) /* 111 = priority level 7 for pin INT8 (higher priority) */
#define IPL8_6 ( BIT2 | BIT1 ) /* 110 = priority level 6 for pin INT8 */
#define IPL8_5 ( BIT2 | BIT0 ) /* 101 = priority level 5 for pin INT8 */
#define IPL8_4 ( BIT2 ) /* 100 = priority level 4 for pin INT8 */
#define IPL8_3 ( BIT1 | BIT0 ) /* 011 = priority level 3 for pin INT8 */
#define IPL8_2 ( BIT1 ) /* 010 = priority level 2 for pin INT8 */
#define IPL8_1 ( BIT0 ) /* 001 = priority level 1 for pin INT8 (lower priority) */
#define IPL8_0 ZEROS /* 000 = priority level 0 for pin INT8 (interrupt disabled) */
#define IPL9_7 ( BIT6 | BIT5 | BIT4 ) /* 111 = priority level 7 for pin INT9 (higher priority) */
#define IPL9_6 ( BIT6 | BIT5 ) /* 110 = priority level 6 for pin INT9 */
#define IPL9_5 ( BIT6 | BIT4 ) /* 101 = priority level 5 for pin INT9 */
#define IPL9_4 ( BIT6 ) /* 100 = priority level 4 for pin INT9 */
#define IPL9_3 ( BIT5 | BIT4 ) /* 011 = priority level 3 for pin INT9 */
#define IPL9_2 ( BIT5 ) /* 010 = priority level 2 for pin INT9 */
#define IPL9_1 ( BIT4 ) /* 001 = priority level 1 for pin INT9 (lower priority) */
#define IPL9_0 ZEROS /* 000 = priority level 0 for pin INT9 (interrupt disabled) */
#define IPL10_7 ( BIT10 | BIT9 | BIT8 ) /* 111 = priority level 7 for pin INT10 (higher priority) */
#define IPL10_6 ( BIT10 | BIT9 ) /* 110 = priority level 6 for pin INT10 */
#define IPL10_5 ( BIT10 | BIT8 ) /* 101 = priority level 5 for pin INT10 */
#define IPL10_4 ( BIT10 ) /* 100 = priority level 4 for pin INT10 */
#define IPL10_3 ( BIT9 | BIT8 ) /* 011 = priority level 3 for pin INT10 */
#define IPL10_2 ( BIT9 ) /* 010 = priority level 2 for pin INT10 */
#define IPL10_1 ( BIT8 ) /* 001 = priority level 1 for pin INT10(lower priority) */
#define IPL10_0 ZEROS /* 000 = priority level 0 for pin INT10(interrupt disabled) */
#define IPL11_7 ( BIT14 | BIT13 | BIT12 ) /* 111 = priority level 7 for pin INT11 (higher priority) */
#define IPL11_6 ( BIT14 | BIT13 ) /* 110 = priority level 6 for pin INT11 */
#define IPL11_5 ( BIT14 | BIT12 ) /* 101 = priority level 5 for pin INT11 */
#define IPL11_4 ( BIT14 ) /* 100 = priority level 4 for pin INT11 */
#define IPL11_3 ( BIT13 | BIT12 ) /* 011 = priority level 3 for pin INT11 */
#define IPL11_2 ( BIT13 ) /* 010 = priority level 2 for pin INT11 */
#define IPL11_1 ( BIT12 ) /* 001 = priority level 1 for pin INT11(lower priority) */
#define IPL11_0 ZEROS /* 000 = priority level 0 for pin INT11(interrupt disabled) */
#define IPL12_7 ( BIT2 | BIT1 | BIT0 ) /* 111 = priority level 7 for pin INT12 (higher priority) */
#define IPL12_6 ( BIT2 | BIT1 ) /* 110 = priority level 6 for pin INT12 */
#define IPL12_5 ( BIT2 | BIT0 ) /* 101 = priority level 5 for pin INT12 */
#define IPL12_4 ( BIT2 ) /* 100 = priority level 4 for pin INT12 */
#define IPL12_3 ( BIT1 | BIT0 ) /* 011 = priority level 3 for pin INT12 */
#define IPL12_2 ( BIT1 ) /* 010 = priority level 2 for pin INT12 */
#define IPL12_1 ( BIT0 ) /* 001 = priority level 1 for pin INT12 (lower priority) */
#define IPL12_0 ZEROS /* 000 = priority level 0 for pin INT12 (interrupt disabled) */
#define IPL13_7 ( BIT6 | BIT5 | BIT4 ) /* 111 = priority level 7 for pin INT13 (higher priority) */
#define IPL13_6 ( BIT6 | BIT5 ) /* 110 = priority level 6 for pin INT13 */
#define IPL13_5 ( BIT6 | BIT4 ) /* 101 = priority level 5 for pin INT13 */
#define IPL13_4 ( BIT6 ) /* 100 = priority level 4 for pin INT13 */
#define IPL13_3 ( BIT5 | BIT4 ) /* 011 = priority level 3 for pin INT13 */
#define IPL13_2 ( BIT5 ) /* 010 = priority level 2 for pin INT13 */
#define IPL13_1 ( BIT4 ) /* 001 = priority level 1 for pin INT13 (lower priority) */
#define IPL13_0 ZEROS /* 000 = priority level 0 for pin INT13 (interrupt disabled) */
#define IPL14_7 ( BIT10 | BIT9 | BIT8 ) /* 111 = priority level 7 for pin INT14 (higher priority) */
#define IPL14_6 ( BIT10 | BIT9 ) /* 110 = priority level 6 for pin INT14 */
#define IPL14_5 ( BIT10 | BIT8 ) /* 101 = priority level 5 for pin INT14 */
#define IPL14_4 ( BIT10 ) /* 100 = priority level 4 for pin INT14 */
#define IPL14_3 ( BIT9 | BIT8 ) /* 011 = priority level 3 for pin INT14 */
#define IPL14_2 ( BIT9 ) /* 010 = priority level 2 for pin INT14 */
#define IPL14_1 ( BIT8 ) /* 001 = priority level 1 for pin INT14 (lower priority) */
#define IPL14_0 ZEROS /* 000 = priority level 0 for pin INT14 (interrupt disabled) */
/* IMR */
#define IT_MASK_LEVEL0 ZEROS /* Interrupt mask level 0 */
#define IT_MASK_LEVEL1 ( BIT0 ) /* Interrupt mask level 1 */
#define IT_MASK_LEVEL2 ( BIT1 ) /* Interrupt mask level 2 */
#define IT_MASK_LEVEL3 ( BIT1 | BIT0 ) /* Interrupt mask level 3 */
#define IT_MASK_LEVEL4 ( BIT2 ) /* Interrupt mask level 4 */
#define IT_MASK_LEVEL5 ( BIT2 | BIT0 ) /* Interrupt mask level 5 */
#define IT_MASK_LEVEL6 ( BIT2 | BIT1 ) /* Interrupt mask level 6 */
#define IT_MASK_LEVEL7 ( BIT2 | BIT1 | BIT0 ) /* Interrupt mask level 7 */
#define REV ( BIT3 ) /* Relocate Exception Vector */
/* IID */
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