reg5087.ho

这是用Labwindows开发的一个RF test程序。 用于日本机种的组装后ANT 测试。

                                        /* it must be cleared by software                                      */
#define U0_RME          ( BIT1 )        /* 1 : Enable the register match function  */
                                        /* 0 : Disable the register match function */
#define U0_FFULL        ( BIT0 )        /* FIFO full flag */




/* PCF5087_U0BCON */

#define U0_FLOW         ( BIT0 )        /* 0 : hardware control of CTS/RTS lines */
                                        /* 1 : software control of CTS/RTS lines */
#define	BST	        ( BIT1 )	/* 0 : stop baud rate generator */
                                        /* 1 : start baud rate generator after loading of the reload */
#define U0_BST	        ( BIT1 )	/* 0 : stop baud rate generator */
                                        /* 1 : start baud rate generator after loading of the reload */
#define U0_CTS          ( BIT2 )        /* Read only : input state of CTS0_N pin */
#define U0_RTS          ( BIT3 )        /* 0 : RTS0_N pin driven low */
                                        /* 1 : RTS0_N pin driven high */


/*------------*/
/* UART1 UNIT */
/*------------*/


#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#if !defined(__PCF50872__)
#define PCF5087_U1SCON1		*( ( volatile u8 *) ( 0xFFFF9103 ) )
#define PCF5087_U1SCON2 	*( ( volatile u8 *) ( 0xFFFF9102 ) )
#define PCF5087_U1BCON  	*( ( volatile u8 *) ( 0xFFFF910F ) )
#define PCF5087_U1BREGH  	*( ( volatile u8 *) ( 0xFFFF910A ) )
#define PCF5087_U1BREGL  	*( ( volatile u8 *) ( 0xFFFF910B ) )
#define PCF5087_U1SBUF		*( ( volatile u8 *) ( 0xFFFF9107 ) )
#else
#define PCF5087_U1SCON1         *( ( volatile u8 *) ( 0xFFFF9103 ) )
#define PCF5087_U1SCON2         *( ( volatile u8 *) ( 0xFFFF9102 ) )
#define PCF5087_U1SCON3         *( ( volatile u8 *) ( 0xFFFF9107 ) )
#define PCF5087_U1SCON4         *( ( volatile u8 *) ( 0xFFFF9106 ) )
#define PCF5087_U1BCON          *( ( volatile u8 *) ( 0xFFFF910B ) )
#define PCF5087_U1BREGH         *( ( volatile u8 *) ( 0xFFFF910E ) )
#define PCF5087_U1BREGL         *( ( volatile u8 *) ( 0xFFFF910F ) )
#define PCF5087_U1SBUF          *( ( volatile u8 *) ( 0xFFFF9113 ) )
#define PCF5087_U1RM            *( ( volatile u8 *) ( 0xFFFF9117 ) )
#define PCF5087_U1RM_A          *( ( volatile u8 *) ( 0xFFFF911B ) )
#endif /* #if defined(__PCF50872__) */
#endif

/* PCF5087_U1SCON1 */

#define U1_MODE3	(  BIT7 |  BIT6 )	/* shift register CLK/6 */
#define U1_MODE2	(  BIT7         )	/* 8-bit UART BGCLK0-1 */
#define U1_MODE1        (          BIT6 )	/* 9-bit UART CLK/16 */
#define U1_MODE0	ZEROS           	/* 9-bit UART BGCLK0-1 
						   RESET STATE */
#define	U1_SM2		( BIT5 )        /* Multiprocessor bit - RESET STATE = 0 */
#define	U1_REN		( BIT4 )	/* Receive enable - RESET STATE = 0. 
					   The receive is enabled when REN is set */
#define	U1_TB8		( BIT3 )	/* Transmit extra bit: 9th data bit that will be transmitted in mode 2 and 3 */
					/* RESET STATE = 0 */
#define	U1_RB8		( BIT2 )	/* Receive extra bit: 9th data bit that will be received in mode 2 and 3 */
					/* in mode 1 if SM2 = 0, RB8 is the stop bit wich is received */
					/* RESET STATE = 0 */
#define	U1_TI		( BIT1 )	/* transmit interrupt flag, set by hardware at the end of the 8th bit time */
					/* in mode 0, or halfway through the stop bit in other modes */
#define U1_RI		( BIT0 )	/* receive interrupt flag, set by hardware at the end of the 8th bit time */
					/* in mode 0, or halfway through the stop bit in other modes */


/* PCF5087_U1SCON2 */

#define U1_FEF          ( BIT7 )                 /* Framing Error Flag */
#define U1_OEF          ( BIT6 )                 /* Overrun Error Flag */
#define U1_PEF          ( BIT5)                 /* Parity Error Flag  */
#define U1_FEN          ( BIT4 )                 /* Enable Framing Error Check bit */
#define U1_OEN          ( BIT3 )                 /* Enable Overrun Error Check bit */
#define U1_EVENP        ( BIT1 )                 /* even parity   */
#define U1_PE           ( BIT0 )                 /* Parity Enable Bit */
#define U1_ODDP         ZEROS                    /* odd parity    */ /*RESET STATE */



/* PCF5087_U0SCON3 */

#define U1_SIREN        ( BIT7 )        /* 0 : No SIR interface function for TxD0 and RxD0 */
                                        /* 1 : Pulse shaping function used in IrDA standard application */
#define U1_LOOP         ( BIT4 )        /* set channel mode , RESET STATE 0 */
                                        /* LOOP = 0 : normal mode, LOOP = 1 : local loopback */
#define U1_BI           ( BIT3 )        /* break interrupt indicator */
#define U1_BEN          ( BIT2 )        /* 0 : Break detection disable */
                                        /* 1 : Break detection enable  */
#define U1_SB           ( BIT1 )        /* Break control bit */
                                        /* 0 : force a break condition ; 1 : disabled break condition*/
#define U1_STB          ( BIT0 )        /* The Number of stop bits transmitted and received */
                                        /* U0STB = 0 : One stop bit                         */
                                        /* U0STB = 1 : Two stop bit                         */
/* PCF5087_U0SCON4 */

#define U1_RMF_A        ( BIT6 )        /* Alternative reception match flag : set at the reception of a matching character */
                                        /* it must be cleared by software                                      */
#define U1_RME_A        ( BIT5 )        /* 1 : Enable the alternative reception match function  */
                                        /* 0 : Disable the alternative reception match function */
#define U1_WUPF		( BIT4 )

#define U1_WUPEN	( BIT3)

#define U1_RMF          ( BIT2 )        /* Reception match flag : set at the reception of a matching character */
                                        /* it must be cleared by software                                      */
#define U1_RME          ( BIT1 )        /* 1 : Enable the reception match function  */
                                        /* 0 : Disable the reception match function */
#define U1_FFULL        ( BIT0 )        /* FIFO full flag */

/* PCF5087_U1BCON */

#define U1_BST	        ( BIT1 )	/* 0 : stop baud rate generator */
                                        /* 1 : start baud rate generator after loading of the reload */


/**********************************************************************/

/*----------*/
/* OOL UNIT */
/*----------*/

#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_OOLC   *( (volatile u16 *)(0xFFFF9402) )
#define PCF5087_STOP   *( (volatile u8  *)(0xFFFF9407) )
#if defined(__PCF50872__)
#define PCF5087_WDTIM  *( (volatile u16 *)(0xFFFF940A) )
#else
#define PCF5087_WDTIM  *( (volatile u8  *)(0xFFFF940B) )
#endif /* #if defined(__PCF50872__) */
#endif

/* PCF5087_OOLC */

#define AUXON_LH      ( BIT0  )    /* ON_OFF_STAT interrupt requested from Low to High transition */
#define AUXON_HL      ( BIT1  )    /* ON_OFF_STAT interrupt requested from High to Low transition */
#define ONKEY         ( BIT2  )    /* ON_OFF_STAT interrupt requested from a positive edge at ONKEY */
#define LOWVOLT       ( BIT3  )    /* ON_OFF_STAT interrupt requested from a positive edge at LOWVOLT_N */
#define RTCINT        ( BIT4  )    /* ON_OFF_STAT interrupt requested from the RTC */
#define SWOFF         ( BIT5  )    /* 1 : start switch off procedure */
#define WDT           ( BIT6  )    /* 1 : watchdog has expired */
#define RTC_RST_N     ( BIT8  )    /* 0 : RTC reset active RST_N = LOW */
                                   /* 1 : RTC reset inactive RST_N = KIGH */
#define RSTN          ( BIT9  )    /* 0 : RST_N was not active during POWON = LOW */
                                   /* 1 : RST_N was active during POWON = LOW */
#define RSTN_ACTIVE   ( BIT10 )    /* 0 : SC peripheral reset and RST_N = 0 */
                                   /* 1 : SC peripheral reset and RST_N = 1 */
#define AUXON_LEVEL   ( BIT11 )    /* Level of the AUXON pin after debouncing */
                                   /* 0 : AUXON pin at 0 */
                                   /* 1 : AUXON pin at 1 */                 

#define CLEAR_AUXON_LH    0x000E
#define CLEAR_AUXON_HL    0x000D
#define CLEAR_AUXON_LH_HL 0x000C
#define CLEAR_ONKEY       0x000B
#define CLEAR_LOWVOLT     0x0007


/* PCF5087_WDTIM */

#define WDT_STAT      ( BIT7 )     /* Watchdog timer has been loaded, wachdog is enabled */


/**********************************************************************/

/*-----------*/
/* PIO UNIT */
/*----------*/

#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_PIOS	*( (volatile u8  *) ( 0xFFFF8303) )
#define PCF5087_SPI	*( (volatile u16 *) ( 0xFFFF8306) )
#define PCF5087_SPO	*( (volatile u16 *) ( 0xFFFF830A) )
#endif

#define HWRQ_EN         ( BIT2 )
#define HRRQ_EN         ( BIT3 )
#define WATCHDOG_EN     ( BIT4 )


/**********************************************************************/

/*-----------*/
/* GPIO UNIT */
/*-----------*/

#if defined (__arm)  || defined(_LABWIN32) || defined(__BORLANDC__)
#if defined(__PCF50872__)
#define PCF5087_GPIOCON *( (volatile u16  *) ( 0xFFFF8402) )
#else
#define PCF5087_GPIOCON	*( (volatile u8  *) ( 0xFFFF8403) )
#endif /* #if defined(__PCF50872__) */
#define PCF5087_GPIODIR	*( (volatile u16 *) ( 0xFFFF8406) )
#define PCF5087_GPIODAT	*( (volatile u16 *) ( 0xFFFF840A) )
#endif

#define GPIO9_EXT1      ( BIT0  )
#define GPIO10_EXT2     ( BIT1  )
#define GPIO8_PWM01     ( BIT2  )
#define GPIO3_FRAME     ( BIT3  )
#define GPIO6_DSPREQ    ( BIT4  )
#define EXT1_INT        ( BIT5  )
#define EXT2_INT        ( BIT6  )
#define EXT3_INT        ( BIT7  )
#define EXT1_NDEB       ( BIT8  )
#define EXT2_NDEB       ( BIT9  )
#define EXT3_NDEB       ( BIT10 )
#define GPIO7_EXT3      ( BIT11 )
#define EXT3_HIGH2LOW   ( BIT12 )
#define EXT3_LOW2HIGH   ( BIT13 )

#define EXT1_HIGH2LOW   ( BIT11 )
#define EXT1_LOW2HIGH   ( BIT12 )
#define EXT2_HIGH2LOW   ( BIT13 )
#define EXT2_LOW2HIGH   ( BIT14 )